2020-05-24 00:02:54 +02:00
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#include <Arduino.h>
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2020-05-26 13:44:02 +02:00
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#include "Hardware.h"
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2020-05-24 00:02:54 +02:00
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#include "DCCWaveform.h"
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#include "DIAG.h"
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2020-05-26 18:06:15 +02:00
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#include "Railcom.h"
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2020-05-26 13:44:02 +02:00
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DCCWaveform DCCWaveform::mainTrack(PREAMBLE_BITS_MAIN, true);
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DCCWaveform DCCWaveform::progTrack(PREAMBLE_BITS_PROG, false);
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2020-05-24 00:02:54 +02:00
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2020-06-06 12:11:03 +02:00
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2020-05-24 00:02:54 +02:00
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void DCCWaveform::begin() {
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2020-05-26 13:44:02 +02:00
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Hardware::init();
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Hardware::setCallback(58, interruptHandler);
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mainTrack.beginTrack();
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progTrack.beginTrack();
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2020-05-24 00:02:54 +02:00
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}
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2020-05-26 13:44:02 +02:00
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void DCCWaveform::loop() {
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mainTrack.checkPowerOverload();
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progTrack.checkPowerOverload();
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}
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2020-05-24 00:02:54 +02:00
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// static //
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void DCCWaveform::interruptHandler() {
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2020-05-26 13:44:02 +02:00
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// call the timer edge sensitive actions for progtrack and maintrack
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bool mainCall2 = mainTrack.interrupt1();
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bool progCall2 = progTrack.interrupt1();
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// call (if necessary) the procs to get the current bits
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// these must complete within 50microsecs of the interrupt
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// but they are only called ONCE PER BIT TRANSMITTED
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// after the rising edge of the signal
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if (mainCall2) mainTrack.interrupt2();
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if (progCall2) progTrack.interrupt2();
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2020-05-24 00:02:54 +02:00
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}
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// An instance of this class handles the DCC transmissions for one track. (main or prog)
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// Interrupts are marshalled via the statics.
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// A track has a current transmit buffer, and a pending buffer.
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2020-05-26 13:44:02 +02:00
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// When the current buffer is exhausted, either the pending buffer (if there is one waiting) or an idle buffer.
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2020-05-24 00:02:54 +02:00
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// This bitmask has 9 entries as each byte is trasmitted as a zero + 8 bits.
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2020-05-26 13:44:02 +02:00
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const byte bitMask[] = {0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01};
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DCCWaveform::DCCWaveform( byte preambleBits, bool isMain) {
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// establish appropriate pins
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isMainTrack = isMain;
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packetPending = false;
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memcpy(transmitPacket, idlePacket, sizeof(idlePacket));
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state = 0;
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requiredPreambles = preambleBits;
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bytes_sent = 0;
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bits_sent = 0;
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nextSampleDue = 0;
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}
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void DCCWaveform::beginTrack() {
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setPowerMode(POWERMODE::ON);
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}
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POWERMODE DCCWaveform::getPowerMode() {
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2020-05-24 00:02:54 +02:00
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return powerMode;
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2020-05-26 13:44:02 +02:00
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}
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void DCCWaveform::setPowerMode(POWERMODE mode) {
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powerMode = mode;
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Hardware::setPower(isMainTrack, mode == POWERMODE::ON);
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if (mode == POWERMODE::ON) delay(200);
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}
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2020-05-24 00:02:54 +02:00
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void DCCWaveform::checkPowerOverload() {
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if (millis() < nextSampleDue) return;
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int delay;
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2020-05-24 00:02:54 +02:00
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switch (powerMode) {
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case POWERMODE::OFF:
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delay = POWER_SAMPLE_OFF_WAIT;
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break;
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case POWERMODE::ON:
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// Check current
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lastCurrent = Hardware::getCurrentMilliamps(isMainTrack);
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if (lastCurrent < POWER_SAMPLE_MAX) delay = POWER_SAMPLE_ON_WAIT;
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else {
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setPowerMode(POWERMODE::OVERLOAD);
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DIAG(F("\n*** %s TRACK POWER OVERLOAD current=%d max=%d ***\n"), isMainTrack ? "MAIN" : "PROG", lastCurrent, POWER_SAMPLE_MAX);
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delay = POWER_SAMPLE_OVERLOAD_WAIT;
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}
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break;
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case POWERMODE::OVERLOAD:
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// Try setting it back on after the OVERLOAD_WAIT
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setPowerMode(POWERMODE::ON);
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delay = POWER_SAMPLE_ON_WAIT;
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break;
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default:
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delay = 999; // cant get here..meaningless statement to avoid compiler warning.
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}
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nextSampleDue = millis() + delay;
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}
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// process time-edge sensitive part of interrupt
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// return true if second level required
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2020-05-24 00:02:54 +02:00
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bool DCCWaveform::interrupt1() {
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// NOTE: this must consume transmission buffers even if the power is off
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// otherwise can cause hangs in main loop waiting for the pendingBuffer.
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switch (state) {
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case 0: // start of bit transmission
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Hardware::setSignal(isMainTrack, HIGH);
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checkRailcom();
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state = 1;
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2020-05-24 11:27:33 +02:00
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return true; // must call interrupt2 to set currentBit
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2020-05-24 00:02:54 +02:00
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2020-05-24 11:27:33 +02:00
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case 1: // 58us after case 0
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if (currentBit) {
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Hardware::setSignal(isMainTrack, LOW);
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state = 0;
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}
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else state = 2;
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break;
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2020-05-24 11:27:33 +02:00
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case 2: // 116us after case 0
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Hardware::setSignal(isMainTrack, LOW);
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state = 3;
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break;
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case 3: // finished sending zero bit
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state = 0;
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break;
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}
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return false;
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2020-05-24 00:02:54 +02:00
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}
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2020-05-24 10:07:54 +02:00
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2020-05-24 00:02:54 +02:00
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void DCCWaveform::interrupt2() {
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// set currentBit to be the next bit to be sent.
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2020-05-24 00:02:54 +02:00
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if (remainingPreambles > 0 ) {
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currentBit = true;
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remainingPreambles--;
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return;
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}
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// beware OF 9-BIT MASK generating a zero to start each byte
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currentBit = transmitPacket[bytes_sent] & bitMask[bits_sent];
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bits_sent++;
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2020-05-26 13:44:02 +02:00
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// If this is the last bit of a byte, prepare for the next byte
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if (bits_sent == 9) { // zero followed by 8 bits of a byte
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//end of Byte
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bits_sent = 0;
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bytes_sent++;
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// if this is the last byte, prepere for next packet
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if (bytes_sent >= transmitLength) {
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// end of transmission buffer... repeat or switch to next message
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bytes_sent = 0;
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remainingPreambles = requiredPreambles;
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if (transmitRepeats > 0) {
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transmitRepeats--;
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}
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else if (packetPending) {
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// Copy pending packet to transmit packet
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for (int b = 0; b < pendingLength; b++) transmitPacket[b] = pendingPacket[b];
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transmitLength = pendingLength;
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transmitRepeats = pendingRepeats;
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packetPending = false;
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sentResetsSincePacket=0;
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}
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else {
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// Fortunately reset and idle packets are the same length
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memcpy( transmitPacket, isMainTrack ? idlePacket : resetPacket, sizeof(idlePacket));
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transmitLength = sizeof(idlePacket);
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transmitRepeats = 0;
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sentResetsSincePacket++;
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}
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}
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}
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2020-05-26 13:44:02 +02:00
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}
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2020-05-24 11:27:33 +02:00
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void DCCWaveform::checkRailcom() {
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if (isMainTrack && RAILCOM_CUTOUT) {
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byte preamble = PREAMBLE_BITS_MAIN - remainingPreambles;
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if (preamble == RAILCOM_PREAMBLES_BEFORE_CUTOUT) {
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Railcom::startCutout();
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}
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}
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2020-05-24 11:27:33 +02:00
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}
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2020-05-26 13:44:02 +02:00
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// Wait until there is no packet pending, then make this pending
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void DCCWaveform::schedulePacket(const byte buffer[], byte byteCount, byte repeats) {
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if (byteCount >= MAX_PACKET_SIZE) return; // allow for chksum
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while (packetPending);
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byte checksum = 0;
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for (int b = 0; b < byteCount; b++) {
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checksum ^= buffer[b];
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pendingPacket[b] = buffer[b];
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}
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pendingPacket[byteCount] = checksum;
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pendingLength = byteCount + 1;
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pendingRepeats = repeats;
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packetPending = true;
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}
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2020-05-26 19:34:54 +02:00
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// Wait until there is no packet pending, then make this pending
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bool DCCWaveform::schedulePacketWithAck(const byte buffer[], byte byteCount, byte repeats) {
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if (isMainTrack) return false;
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int baseline=0;
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for (int i=0;i<ACK_BASELINE_SAMPLES;i++) {
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baseline += Hardware::getCurrentMilliamps(isMainTrack);
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}
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baseline/=ACK_BASELINE_SAMPLES;
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int upTrigger=baseline+ACK_MIN_PULSE;
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DIAG(F("\nACK baseline=%d upT=%d "),baseline, upTrigger);
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schedulePacket(buffer,byteCount,repeats);
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while (packetPending); // wait until transmitter has started transmitting the message
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2020-05-26 13:44:02 +02:00
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unsigned long timeout = millis() + ACK_TIMEOUT;
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int maxCurrent = 0;
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bool result = false;
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int upsamples = 0;
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2020-05-26 13:44:02 +02:00
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2020-05-26 19:34:54 +02:00
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// Monitor looking for an ack signal rise of at least 60mA but keep going for the timeout
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while (timeout > millis()) {
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int current = Hardware::getCurrentMilliamps(isMainTrack);
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maxCurrent = max(maxCurrent, current);
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if (current>upTrigger) {
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result=true;
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upsamples++;
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}
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2020-05-26 19:34:54 +02:00
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}
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2020-05-26 13:44:02 +02:00
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// The following DIAG is really useful as it can show how long and how far the
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// current changes during an ACK from the decoder.
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DIAG(F("ack=%d max=%d, up=%d"), result, maxCurrent, upsamples);
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return result;
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}
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2020-06-02 14:20:36 +02:00
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int DCCWaveform::getLastCurrent() {
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return lastCurrent;
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}
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