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https://github.com/DCC-EX/CommandStation-EX.git
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static constants
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@ -57,14 +57,6 @@ class I2CRailcom : public IODevice {
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private:
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// SC16IS752 defines
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uint8_t _UART_CH=0x00;
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// Communication parameters for the DFPlayer are fixed at 8 bit, No parity, 1 stopbit
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const uint8_t WORD_LEN = 0x03; // Value LCR bit 0,1
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const uint8_t STOP_BIT = 0x00; // Value LCR bit 2
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const uint8_t PARITY_ENA = 0x00; // Value LCR bit 3
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const uint8_t PARITY_TYPE = 0x00; // Value LCR bit 4
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const uint32_t BAUD_RATE = 250000;
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const uint8_t PRESCALER = 0x01; // Value MCR bit 7
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const unsigned long SC16IS752_XTAL_FREQ_RAILCOM = 16000000; // Baud rate for Railcom signal
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byte _inbuf[65];
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byte _outbuf[2];
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public:
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@ -155,10 +147,18 @@ private:
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// DLL least significant part of divisor
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//
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// BAUD_RATE, WORD_LEN, STOP_BIT, PARITY_ENA and PARITY_TYPE have been defined and initialized
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//
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//
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// Communication parameters 8 bit, No parity, 1 stopbit
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static const uint8_t WORD_LEN = 0x03; // Value LCR bit 0,1
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static const uint8_t STOP_BIT = 0x00; // Value LCR bit 2
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static const uint8_t PARITY_ENA = 0x00; // Value LCR bit 3
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static const uint8_t PARITY_TYPE = 0x00; // Value LCR bit 4
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static const uint32_t BAUD_RATE = 250000;
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static const uint8_t PRESCALER = 0x01; // Value MCR bit 7
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static const unsigned long SC16IS752_XTAL_FREQ_RAILCOM = 16000000; // Baud rate for Railcom signal
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static const uint16_t _divisor = (SC16IS752_XTAL_FREQ_RAILCOM / PRESCALER) / (BAUD_RATE * 16);
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void Init_SC16IS752(){
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//uint16_t _divisor = (SC16IS752_XTAL_FREQ / PRESCALER) / (BAUD_RATE * 16);
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const uint16_t _divisor = (SC16IS752_XTAL_FREQ_RAILCOM / PRESCALER) / (BAUD_RATE * 16); // Calculate _divisor for baudrate
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if (_UART_CH==0) {
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// only reset on channel 0}
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@ -168,13 +168,16 @@ private:
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UART_WriteRegister(REG_FCR, 0x07,false); // Reset FIFO, clear RX & TX FIFO (write only)
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UART_WriteRegister(REG_MCR, 0x00); // Set MCR to all 0, includes Clock divisor
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UART_WriteRegister(REG_LCR, 0x80 | WORD_LEN | STOP_BIT | PARITY_ENA | PARITY_TYPE); // Divisor latch enabled
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UART_WriteRegister(REG_LCR, 0x80); // Divisor latch enabled
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UART_WriteRegister(REG_DLL, _divisor); // Write DLL
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UART_WriteRegister(REG_DLH, (uint8_t)(_divisor >> 8)); // Write DLH
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UART_WriteRegister(REG_LCR, UART_ReadRegister(REG_LCR) & 0x7F); // Divisor latch disabled
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UART_WriteRegister(REG_LCR, WORD_LEN | STOP_BIT | PARITY_ENA | PARITY_TYPE); // Divisor latch disabled
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UART_WriteRegister(REG_FCR, 0x07,false); // Reset FIFO, clear RX & TX FIFO (write only)
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if (_deviceState==DEVSTATE_INITIALISING) {
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DIAG(F("UART %d init complete"),_UART_CH);
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}
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}
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}
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