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https://github.com/DCC-EX/CommandStation-EX.git
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including timer library into code source
This commit is contained in:
parent
b81b7ee27f
commit
10a4d1632a
@ -32,7 +32,7 @@
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#include "DCCTimer.h"
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#include "DIAG.h"
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#include "Portenta_H7_TimerInterrupt.h"
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#include "GigaHardwareTimer.h"
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#include <Arduino_AdvancedAnalog.h>
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//#include "config.h"
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///////////////////////////////////////////////////////////////////////////////////////////////
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2003
GigaHardwareTimer.cpp
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2003
GigaHardwareTimer.cpp
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File diff suppressed because it is too large
Load Diff
220
GigaHardwareTimer.h
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220
GigaHardwareTimer.h
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@ -0,0 +1,220 @@
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/****************************************************************************************************************************
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HardwareTimer.h
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For Portenta_H7 boards
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Written by Khoi Hoang
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Built by Khoi Hoang https://github.com/khoih-prog/Portenta_H7_TimerInterrupt
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Licensed under MIT license
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Now even you use all these new 16 ISR-based timers,with their maximum interval practically unlimited (limited only by
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unsigned long miliseconds), you just consume only one Portenta_H7 STM32 timer and avoid conflicting with other cores' tasks.
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The accuracy is nearly perfect compared to software timers. The most important feature is they're ISR-based timers
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Therefore, their executions are not blocked by bad-behaving functions / tasks.
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This important feature is absolutely necessary for mission-critical tasks.
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Version: 1.4.0
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Version Modified By Date Comments
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------- ----------- ---------- -----------
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1.2.1 K.Hoang 15/09/2021 Initial coding for Portenta_H7
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1.3.0 K.Hoang 17/09/2021 Add PWM features and examples
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1.3.1 K.Hoang 21/09/2021 Fix warnings in PWM examples
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1.4.0 K.Hoang 22/01/2022 Fix `multiple-definitions` linker error. Fix bug
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*****************************************************************************************************************************/
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// Modified from stm32 core v2.0.0
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/*
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Copyright (c) 2017 Daniel Fekete
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Copyright (c) 2019 STMicroelectronics
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Modified to support Arduino_Core_STM32
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef GIGAHARDWARETIMER_H_
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#define GIGAHARDWARETIMER_H_
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#if defined(ARDUINO_GIGA)
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/* Includes ------------------------------------------------------------------*/
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#include "Gigatimer.h"
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#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY)
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#define TIMER_CHANNELS 4 // channel5 and channel 6 are not considered here has they don't have gpio output and they don't have interrupt
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typedef enum
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{
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TIMER_DISABLED, // == TIM_OCMODE_TIMING no output, useful for only-interrupt
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// Output Compare
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TIMER_OUTPUT_COMPARE, // == Obsolete, use TIMER_DISABLED instead. Kept for compatibility reason
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TIMER_OUTPUT_COMPARE_ACTIVE, // == TIM_OCMODE_ACTIVE pin is set high when counter == channel compare
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TIMER_OUTPUT_COMPARE_INACTIVE, // == TIM_OCMODE_INACTIVE pin is set low when counter == channel compare
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TIMER_OUTPUT_COMPARE_TOGGLE, // == TIM_OCMODE_TOGGLE pin toggles when counter == channel compare
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TIMER_OUTPUT_COMPARE_PWM1, // == TIM_OCMODE_PWM1 pin high when counter < channel compare, low otherwise
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TIMER_OUTPUT_COMPARE_PWM2, // == TIM_OCMODE_PWM2 pin low when counter < channel compare, high otherwise
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TIMER_OUTPUT_COMPARE_FORCED_ACTIVE, // == TIM_OCMODE_FORCED_ACTIVE pin always high
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TIMER_OUTPUT_COMPARE_FORCED_INACTIVE, // == TIM_OCMODE_FORCED_INACTIVE pin always low
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//Input capture
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TIMER_INPUT_CAPTURE_RISING, // == TIM_INPUTCHANNELPOLARITY_RISING
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TIMER_INPUT_CAPTURE_FALLING, // == TIM_INPUTCHANNELPOLARITY_FALLING
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TIMER_INPUT_CAPTURE_BOTHEDGE, // == TIM_INPUTCHANNELPOLARITY_BOTHEDGE
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// Used 2 channels for a single pin. One channel in TIM_INPUTCHANNELPOLARITY_RISING another channel in TIM_INPUTCHANNELPOLARITY_FALLING.
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// Channels must be used by pair: CH1 with CH2, or CH3 with CH4
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// This mode is very useful for Frequency and Dutycycle measurement
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TIMER_INPUT_FREQ_DUTY_MEASUREMENT,
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TIMER_NOT_USED = 0xFFFF // This must be the last item of this enum
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} TimerModes_t;
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typedef enum
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{
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TICK_FORMAT, // default
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MICROSEC_FORMAT,
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HERTZ_FORMAT,
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} TimerFormat_t;
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typedef enum
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{
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RESOLUTION_1B_COMPARE_FORMAT = 1, // used for Dutycycle: [0 .. 1]
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RESOLUTION_2B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 3]
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RESOLUTION_3B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 7]
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RESOLUTION_4B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 15]
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RESOLUTION_5B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 31]
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RESOLUTION_6B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 63]
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RESOLUTION_7B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 127]
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RESOLUTION_8B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 255]
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RESOLUTION_9B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 511]
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RESOLUTION_10B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 1023]
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RESOLUTION_11B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 2047]
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RESOLUTION_12B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 4095]
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RESOLUTION_13B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 8191]
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RESOLUTION_14B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 16383]
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RESOLUTION_15B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 32767]
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RESOLUTION_16B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 65535]
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TICK_COMPARE_FORMAT = 0x80, // default
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MICROSEC_COMPARE_FORMAT,
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HERTZ_COMPARE_FORMAT,
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PERCENT_COMPARE_FORMAT, // used for Dutycycle
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} TimerCompareFormat_t;
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#ifdef __cplusplus
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#include <functional>
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using callback_function_t = std::function<void(void)>;
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/* Class --------------------------------------------------------*/
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class HardwareTimer
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{
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public:
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HardwareTimer(TIM_TypeDef *instance);
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~HardwareTimer(); // destructor
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void pause(void); // Pause counter and all output channels
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void pauseChannel(uint32_t channel); // Timer is still running but channel (output and interrupt) is disabled
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void resume(void); // Resume counter and all output channels
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void resumeChannel(uint32_t channel); // Resume only one channel
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void setPrescaleFactor(uint32_t prescaler); // set prescaler register (which is factor value - 1)
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uint32_t getPrescaleFactor();
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void setOverflow(uint32_t val, TimerFormat_t format =
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TICK_FORMAT); // set AutoReload register depending on format provided
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uint32_t getOverflow(TimerFormat_t format = TICK_FORMAT); // return overflow depending on format provided
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void setPWM(uint32_t channel, PinName pin, uint32_t frequency, uint32_t dutycycle,
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callback_function_t PeriodCallback = nullptr,
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callback_function_t CompareCallback = nullptr); // Set all in one command freq in HZ, Duty in percentage. Including both interrup.
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void setPWM(uint32_t channel, uint32_t pin, uint32_t frequency, uint32_t dutycycle,
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callback_function_t PeriodCallback = nullptr, callback_function_t CompareCallback = nullptr);
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void setCount(uint32_t val, TimerFormat_t format =
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TICK_FORMAT); // set timer counter to value 'val' depending on format provided
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uint32_t getCount(TimerFormat_t format =
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TICK_FORMAT); // return current counter value of timer depending on format provided
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void setMode(uint32_t channel, TimerModes_t mode,
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PinName pin = NC); // Configure timer channel with specified mode on specified pin if available
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void setMode(uint32_t channel, TimerModes_t mode, uint32_t pin);
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TimerModes_t getMode(uint32_t channel); // Retrieve configured mode
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void setPreloadEnable(bool value); // Configure overflow preload enable setting
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uint32_t getCaptureCompare(uint32_t channel,
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TimerCompareFormat_t format = TICK_COMPARE_FORMAT); // return Capture/Compare register value of specified channel depending on format provided
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void setCaptureCompare(uint32_t channel, uint32_t compare,
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TimerCompareFormat_t format = TICK_COMPARE_FORMAT); // set Compare register value of specified channel depending on format provided
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void setInterruptPriority(uint32_t preemptPriority, uint32_t subPriority); // set interrupt priority
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//Add interrupt to period update
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void attachInterrupt(callback_function_t
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callback); // Attach interrupt callback which will be called upon update event (timer rollover)
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void detachInterrupt(); // remove interrupt callback which was attached to update event
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bool hasInterrupt(); //returns true if a timer rollover interrupt has already been set
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//Add interrupt to capture/compare channel
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void attachInterrupt(uint32_t channel,
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callback_function_t callback); // Attach interrupt callback which will be called upon compare match event of specified channel
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void detachInterrupt(uint32_t
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channel); // remove interrupt callback which was attached to compare match event of specified channel
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bool hasInterrupt(uint32_t channel); //returns true if an interrupt has already been set on the channel compare match
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void timerHandleDeinit(); // Timer deinitialization
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// Refresh() is usefull while timer is running after some registers update
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void refresh(
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void); // Generate update event to force all registers (Autoreload, prescaler, compare) to be taken into account
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uint32_t getTimerClkFreq(); // return timer clock frequency in Hz.
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static void captureCompareCallback(TIM_HandleTypeDef
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*htim); // Generic Caputre and Compare callback which will call user callback
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static void updateCallback(TIM_HandleTypeDef
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*htim); // Generic Update (rollover) callback which will call user callback
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// The following function(s) are available for more advanced timer options
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TIM_HandleTypeDef *getHandle(); // return the handle address for HAL related configuration
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int getChannel(uint32_t channel);
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int getLLChannel(uint32_t channel);
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int getIT(uint32_t channel);
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int getAssociatedChannel(uint32_t channel);
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#if defined(TIM_CCER_CC1NE)
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bool isComplementaryChannel[TIMER_CHANNELS];
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#endif
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private:
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TimerModes_t _ChannelMode[TIMER_CHANNELS];
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timerObj_t _timerObj;
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callback_function_t callbacks[1 +
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TIMER_CHANNELS]; //Callbacks: 0 for update, 1-4 for channels. (channel5/channel6, if any, doesn't have interrupt)
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};
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extern timerObj_t *HardwareTimer_Handle[TIMER_NUM];
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extern timer_index_t get_timer_index(TIM_TypeDef *htim);
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#endif /* __cplusplus */
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#endif // HAL_TIM_MODULE_ENABLED && !HAL_TIM_MODULE_ONLY
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#endif
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#endif // GIGAHARDWARETIMER_H_
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Gigatimer.c
Normal file
950
Gigatimer.c
Normal file
@ -0,0 +1,950 @@
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/****************************************************************************************************************************
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timer.c
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For Portenta_H7 boards
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Written by Khoi Hoang
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Built by Khoi Hoang https://github.com/khoih-prog/Portenta_H7_TimerInterrupt
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Licensed under MIT license
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Now even you use all these new 16 ISR-based timers,with their maximum interval practically unlimited (limited only by
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unsigned long miliseconds), you just consume only one Portenta_H7 STM32 timer and avoid conflicting with other cores' tasks.
|
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The accuracy is nearly perfect compared to software timers. The most important feature is they're ISR-based timers
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Therefore, their executions are not blocked by bad-behaving functions / tasks.
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This important feature is absolutely necessary for mission-critical tasks.
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Version: 1.4.0
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Version Modified By Date Comments
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------- ----------- ---------- -----------
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1.2.1 K.Hoang 15/09/2021 Initial coding for Portenta_H7
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1.3.0 K.Hoang 17/09/2021 Add PWM features and examples
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1.3.1 K.Hoang 21/09/2021 Fix warnings in PWM examples
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1.4.0 K.Hoang 22/01/2022 Fix `multiple-definitions` linker error. Fix bug
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*****************************************************************************************************************************/
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// Modified from stm32 core v2.0.0
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/*
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*******************************************************************************
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Copyright (c) 2019, STMicroelectronics
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All rights reserved.
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This software component is licensed by ST under BSD 3-Clause license,
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the "License"; You may not use this file except in compliance with the
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License. You may obtain a copy of the License at:
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opensource.org/licenses/BSD-3-Clause
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*******************************************************************************
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*/
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#if defined(ARDUINO_GIGA)
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#include "Gigatimer.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY)
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/* Private Functions */
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/* Aim of the function is to get _timerObj pointer using htim pointer */
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/* Highly inspired from magical linux kernel's "container_of" */
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/* (which was not directly used since not compatible with IAR toolchain) */
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timerObj_t *get_timer_obj(TIM_HandleTypeDef *htim)
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{
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timerObj_t *obj;
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obj = (timerObj_t *)((char *)htim - offsetof(timerObj_t, handle));
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return (obj);
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}
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/**
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@brief TIMER Initialization - clock init and nvic init
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@param htim_base: TIM handle
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@retval None
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*/
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void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base)
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{
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timerObj_t *obj = get_timer_obj(htim_base);
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enableTimerClock(htim_base);
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// configure Update interrupt
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HAL_NVIC_SetPriority(getTimerUpIrq(htim_base->Instance), obj->preemptPriority, obj->subPriority);
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HAL_NVIC_EnableIRQ(getTimerUpIrq(htim_base->Instance));
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if (getTimerCCIrq(htim_base->Instance) != getTimerUpIrq(htim_base->Instance))
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{
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// configure Capture Compare interrupt
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HAL_NVIC_SetPriority(getTimerCCIrq(htim_base->Instance), obj->preemptPriority, obj->subPriority);
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HAL_NVIC_EnableIRQ(getTimerCCIrq(htim_base->Instance));
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}
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}
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/**
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@brief TIMER Deinitialization - clock and nvic
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@param htim_base: TIM handle
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@retval None
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*/
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void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim_base)
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{
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disableTimerClock(htim_base);
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HAL_NVIC_DisableIRQ(getTimerUpIrq(htim_base->Instance));
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HAL_NVIC_DisableIRQ(getTimerCCIrq(htim_base->Instance));
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}
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/**
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@brief Initializes the TIM Output Compare MSP.
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@param htim: TIM handle
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@retval None
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*/
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void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
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{
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timerObj_t *obj = get_timer_obj(htim);
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enableTimerClock(htim);
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// configure Update interrupt
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HAL_NVIC_SetPriority(getTimerUpIrq(htim->Instance), obj->preemptPriority, obj->subPriority);
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HAL_NVIC_EnableIRQ(getTimerUpIrq(htim->Instance));
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if (getTimerCCIrq(htim->Instance) != getTimerUpIrq(htim->Instance))
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{
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// configure Capture Compare interrupt
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HAL_NVIC_SetPriority(getTimerCCIrq(htim->Instance), obj->preemptPriority, obj->subPriority);
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HAL_NVIC_EnableIRQ(getTimerCCIrq(htim->Instance));
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}
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}
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/**
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@brief DeInitialize TIM Output Compare MSP.
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@param htim: TIM handle
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@retval None
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*/
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void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
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{
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disableTimerClock(htim);
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HAL_NVIC_DisableIRQ(getTimerUpIrq(htim->Instance));
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HAL_NVIC_DisableIRQ(getTimerCCIrq(htim->Instance));
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}
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/**
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@brief Initializes the TIM Input Capture MSP.
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@param htim: TIM handle
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@retval None
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*/
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void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
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{
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enableTimerClock(htim);
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}
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/**
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@brief DeInitialize TIM Input Capture MSP.
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@param htim: TIM handle
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@retval None
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*/
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void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
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{
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disableTimerClock(htim);
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}
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/* Exported functions */
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/**
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@brief Enable the timer clock
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@param htim: TIM handle
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@retval None
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*/
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void enableTimerClock(TIM_HandleTypeDef *htim)
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{
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// Enable TIM clock
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#if defined(TIM1_BASE)
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if (htim->Instance == TIM1)
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{
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__HAL_RCC_TIM1_CLK_ENABLE();
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}
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#endif
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#if defined(TIM2_BASE)
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if (htim->Instance == TIM2)
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{
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__HAL_RCC_TIM2_CLK_ENABLE();
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}
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#endif
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#if defined(TIM3_BASE)
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if (htim->Instance == TIM3)
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{
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__HAL_RCC_TIM3_CLK_ENABLE();
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}
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#endif
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#if defined(TIM4_BASE)
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if (htim->Instance == TIM4)
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{
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__HAL_RCC_TIM4_CLK_ENABLE();
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}
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#endif
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#if defined(TIM5_BASE)
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if (htim->Instance == TIM5)
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{
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__HAL_RCC_TIM5_CLK_ENABLE();
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}
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#endif
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#if defined(TIM6_BASE)
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|
||||
if (htim->Instance == TIM6)
|
||||
{
|
||||
__HAL_RCC_TIM6_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM7_BASE)
|
||||
|
||||
if (htim->Instance == TIM7)
|
||||
{
|
||||
__HAL_RCC_TIM7_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM8_BASE)
|
||||
|
||||
if (htim->Instance == TIM8)
|
||||
{
|
||||
__HAL_RCC_TIM8_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM9_BASE)
|
||||
|
||||
if (htim->Instance == TIM9)
|
||||
{
|
||||
__HAL_RCC_TIM9_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM10_BASE)
|
||||
|
||||
if (htim->Instance == TIM10)
|
||||
{
|
||||
__HAL_RCC_TIM10_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM11_BASE)
|
||||
|
||||
if (htim->Instance == TIM11)
|
||||
{
|
||||
__HAL_RCC_TIM11_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM12_BASE)
|
||||
|
||||
if (htim->Instance == TIM12)
|
||||
{
|
||||
__HAL_RCC_TIM12_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM13_BASE)
|
||||
|
||||
if (htim->Instance == TIM13)
|
||||
{
|
||||
__HAL_RCC_TIM13_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM14_BASE)
|
||||
|
||||
if (htim->Instance == TIM14)
|
||||
{
|
||||
__HAL_RCC_TIM14_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM15_BASE)
|
||||
|
||||
if (htim->Instance == TIM15)
|
||||
{
|
||||
__HAL_RCC_TIM15_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM16_BASE)
|
||||
|
||||
if (htim->Instance == TIM16)
|
||||
{
|
||||
__HAL_RCC_TIM16_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM17_BASE)
|
||||
|
||||
if (htim->Instance == TIM17)
|
||||
{
|
||||
__HAL_RCC_TIM17_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM18_BASE)
|
||||
|
||||
if (htim->Instance == TIM18)
|
||||
{
|
||||
__HAL_RCC_TIM18_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM19_BASE)
|
||||
|
||||
if (htim->Instance == TIM19)
|
||||
{
|
||||
__HAL_RCC_TIM19_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM20_BASE)
|
||||
|
||||
if (htim->Instance == TIM20)
|
||||
{
|
||||
__HAL_RCC_TIM20_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM21_BASE)
|
||||
|
||||
if (htim->Instance == TIM21)
|
||||
{
|
||||
__HAL_RCC_TIM21_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM22_BASE)
|
||||
|
||||
if (htim->Instance == TIM22)
|
||||
{
|
||||
__HAL_RCC_TIM22_CLK_ENABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Disable the timer clock
|
||||
@param htim: TIM handle
|
||||
@retval None
|
||||
*/
|
||||
void disableTimerClock(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
// Enable TIM clock
|
||||
#if defined(TIM1_BASE)
|
||||
if (htim->Instance == TIM1)
|
||||
{
|
||||
__HAL_RCC_TIM1_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM2_BASE)
|
||||
|
||||
if (htim->Instance == TIM2)
|
||||
{
|
||||
__HAL_RCC_TIM2_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM3_BASE)
|
||||
|
||||
if (htim->Instance == TIM3)
|
||||
{
|
||||
__HAL_RCC_TIM3_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM4_BASE)
|
||||
|
||||
if (htim->Instance == TIM4)
|
||||
{
|
||||
__HAL_RCC_TIM4_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM5_BASE)
|
||||
|
||||
if (htim->Instance == TIM5)
|
||||
{
|
||||
__HAL_RCC_TIM5_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM6_BASE)
|
||||
|
||||
if (htim->Instance == TIM6)
|
||||
{
|
||||
__HAL_RCC_TIM6_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM7_BASE)
|
||||
|
||||
if (htim->Instance == TIM7)
|
||||
{
|
||||
__HAL_RCC_TIM7_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM8_BASE)
|
||||
|
||||
if (htim->Instance == TIM8)
|
||||
{
|
||||
__HAL_RCC_TIM8_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM9_BASE)
|
||||
|
||||
if (htim->Instance == TIM9)
|
||||
{
|
||||
__HAL_RCC_TIM9_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM10_BASE)
|
||||
|
||||
if (htim->Instance == TIM10)
|
||||
{
|
||||
__HAL_RCC_TIM10_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM11_BASE)
|
||||
|
||||
if (htim->Instance == TIM11)
|
||||
{
|
||||
__HAL_RCC_TIM11_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM12_BASE)
|
||||
|
||||
if (htim->Instance == TIM12)
|
||||
{
|
||||
__HAL_RCC_TIM12_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM13_BASE)
|
||||
|
||||
if (htim->Instance == TIM13)
|
||||
{
|
||||
__HAL_RCC_TIM13_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM14_BASE)
|
||||
|
||||
if (htim->Instance == TIM14)
|
||||
{
|
||||
__HAL_RCC_TIM14_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM15_BASE)
|
||||
|
||||
if (htim->Instance == TIM15)
|
||||
{
|
||||
__HAL_RCC_TIM15_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM16_BASE)
|
||||
|
||||
if (htim->Instance == TIM16)
|
||||
{
|
||||
__HAL_RCC_TIM16_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM17_BASE)
|
||||
|
||||
if (htim->Instance == TIM17)
|
||||
{
|
||||
__HAL_RCC_TIM17_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM18_BASE)
|
||||
|
||||
if (htim->Instance == TIM18)
|
||||
{
|
||||
__HAL_RCC_TIM18_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM19_BASE)
|
||||
|
||||
if (htim->Instance == TIM19)
|
||||
{
|
||||
__HAL_RCC_TIM19_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM20_BASE)
|
||||
|
||||
if (htim->Instance == TIM20)
|
||||
{
|
||||
__HAL_RCC_TIM20_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM21_BASE)
|
||||
|
||||
if (htim->Instance == TIM21)
|
||||
{
|
||||
__HAL_RCC_TIM21_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(TIM22_BASE)
|
||||
|
||||
if (htim->Instance == TIM22)
|
||||
{
|
||||
__HAL_RCC_TIM22_CLK_DISABLE();
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
@brief This function return IRQ number corresponding to update interrupt event of timer instance.
|
||||
@param tim: timer instance
|
||||
@retval IRQ number
|
||||
*/
|
||||
IRQn_Type getTimerUpIrq(TIM_TypeDef *tim)
|
||||
{
|
||||
IRQn_Type IRQn = NonMaskableInt_IRQn;
|
||||
|
||||
if (tim != (TIM_TypeDef *)NC)
|
||||
{
|
||||
/* Get IRQn depending on TIM instance */
|
||||
switch ((uint32_t)tim)
|
||||
{
|
||||
#if defined(TIM1_BASE)
|
||||
|
||||
case (uint32_t)TIM1_BASE:
|
||||
IRQn = TIM1_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM2_BASE)
|
||||
|
||||
case (uint32_t)TIM2_BASE:
|
||||
IRQn = TIM2_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM3_BASE)
|
||||
|
||||
case (uint32_t)TIM3_BASE:
|
||||
IRQn = TIM3_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM4_BASE)
|
||||
|
||||
case (uint32_t)TIM4_BASE:
|
||||
IRQn = TIM4_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM5_BASE)
|
||||
|
||||
case (uint32_t)TIM5_BASE:
|
||||
IRQn = TIM5_IRQn;
|
||||
break;
|
||||
#endif
|
||||
|
||||
// KH
|
||||
#if 0
|
||||
#if defined(TIM6_BASE)
|
||||
|
||||
case (uint32_t)TIM6_BASE:
|
||||
IRQn = TIM6_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#endif
|
||||
//////
|
||||
|
||||
#if defined(TIM7_BASE)
|
||||
|
||||
case (uint32_t)TIM7_BASE:
|
||||
IRQn = TIM7_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM8_BASE)
|
||||
|
||||
case (uint32_t)TIM8_BASE:
|
||||
IRQn = TIM8_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM9_BASE)
|
||||
|
||||
case (uint32_t)TIM9_BASE:
|
||||
IRQn = TIM9_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM10_BASE)
|
||||
|
||||
case (uint32_t)TIM10_BASE:
|
||||
IRQn = TIM10_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM11_BASE)
|
||||
|
||||
case (uint32_t)TIM11_BASE:
|
||||
IRQn = TIM11_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM12_BASE)
|
||||
|
||||
case (uint32_t)TIM12_BASE:
|
||||
IRQn = TIM12_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM13_BASE)
|
||||
|
||||
case (uint32_t)TIM13_BASE:
|
||||
IRQn = TIM13_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM14_BASE)
|
||||
|
||||
case (uint32_t)TIM14_BASE:
|
||||
IRQn = TIM14_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM15_BASE)
|
||||
|
||||
case (uint32_t)TIM15_BASE:
|
||||
IRQn = TIM15_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM16_BASE)
|
||||
|
||||
case (uint32_t)TIM16_BASE:
|
||||
IRQn = TIM16_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM17_BASE)
|
||||
|
||||
case (uint32_t)TIM17_BASE:
|
||||
IRQn = TIM17_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM18_BASE)
|
||||
|
||||
case (uint32_t)TIM18_BASE:
|
||||
IRQn = TIM18_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM19_BASE)
|
||||
|
||||
case (uint32_t)TIM19_BASE:
|
||||
IRQn = TIM19_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM20_BASE)
|
||||
|
||||
case (uint32_t)TIM20_BASE:
|
||||
IRQn = TIM20_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM21_BASE)
|
||||
|
||||
case (uint32_t)TIM21_BASE:
|
||||
IRQn = TIM21_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM22_BASE)
|
||||
|
||||
case (uint32_t)TIM22_BASE:
|
||||
IRQn = TIM22_IRQn;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
//_Error_Handler("TIM: Unknown timer IRQn", (int)tim);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return IRQn;
|
||||
}
|
||||
|
||||
/**
|
||||
@brief This function return IRQ number corresponding to Capture or Compare interrupt event of timer instance.
|
||||
@param tim: timer instance
|
||||
@retval IRQ number
|
||||
*/
|
||||
IRQn_Type getTimerCCIrq(TIM_TypeDef *tim)
|
||||
{
|
||||
IRQn_Type IRQn = NonMaskableInt_IRQn;
|
||||
|
||||
if (tim != (TIM_TypeDef *)NC)
|
||||
{
|
||||
/* Get IRQn depending on TIM instance */
|
||||
switch ((uint32_t)tim)
|
||||
{
|
||||
#if defined(TIM1_BASE)
|
||||
|
||||
case (uint32_t)TIM1_BASE:
|
||||
IRQn = TIM1_CC_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM2_BASE)
|
||||
|
||||
case (uint32_t)TIM2_BASE:
|
||||
IRQn = TIM2_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM3_BASE)
|
||||
|
||||
case (uint32_t)TIM3_BASE:
|
||||
IRQn = TIM3_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM4_BASE)
|
||||
|
||||
case (uint32_t)TIM4_BASE:
|
||||
IRQn = TIM4_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM5_BASE)
|
||||
|
||||
case (uint32_t)TIM5_BASE:
|
||||
IRQn = TIM5_IRQn;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
// KH
|
||||
#if defined(TIM6_BASE)
|
||||
|
||||
case (uint32_t)TIM6_BASE:
|
||||
IRQn = TIM6_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#endif
|
||||
//////
|
||||
|
||||
#if defined(TIM7_BASE)
|
||||
|
||||
case (uint32_t)TIM7_BASE:
|
||||
IRQn = TIM7_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM8_BASE)
|
||||
|
||||
case (uint32_t)TIM8_BASE:
|
||||
IRQn = TIM8_CC_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM9_BASE)
|
||||
|
||||
case (uint32_t)TIM9_BASE:
|
||||
IRQn = TIM9_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM10_BASE)
|
||||
|
||||
case (uint32_t)TIM10_BASE:
|
||||
IRQn = TIM10_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM11_BASE)
|
||||
|
||||
case (uint32_t)TIM11_BASE:
|
||||
IRQn = TIM11_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM12_BASE)
|
||||
|
||||
case (uint32_t)TIM12_BASE:
|
||||
IRQn = TIM12_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM13_BASE)
|
||||
|
||||
case (uint32_t)TIM13_BASE:
|
||||
IRQn = TIM13_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM14_BASE)
|
||||
|
||||
case (uint32_t)TIM14_BASE:
|
||||
IRQn = TIM14_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM15_BASE)
|
||||
|
||||
case (uint32_t)TIM15_BASE:
|
||||
IRQn = TIM15_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM16_BASE)
|
||||
|
||||
case (uint32_t)TIM16_BASE:
|
||||
IRQn = TIM16_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM17_BASE)
|
||||
|
||||
case (uint32_t)TIM17_BASE:
|
||||
IRQn = TIM17_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM18_BASE)
|
||||
|
||||
case (uint32_t)TIM18_BASE:
|
||||
IRQn = TIM18_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM19_BASE)
|
||||
|
||||
case (uint32_t)TIM19_BASE:
|
||||
IRQn = TIM19_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM20_BASE)
|
||||
|
||||
case (uint32_t)TIM20_BASE:
|
||||
IRQn = TIM20_CC_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM21_BASE)
|
||||
|
||||
case (uint32_t)TIM21_BASE:
|
||||
IRQn = TIM21_IRQn;
|
||||
break;
|
||||
#endif
|
||||
#if defined(TIM22_BASE)
|
||||
|
||||
case (uint32_t)TIM22_BASE:
|
||||
IRQn = TIM22_IRQn;
|
||||
break;
|
||||
#endif
|
||||
break;
|
||||
|
||||
default:
|
||||
//_Error_Handler("TIM: Unknown timer IRQn", (int)tim);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return IRQn;
|
||||
}
|
||||
|
||||
/**
|
||||
@brief This function return the timer clock source.
|
||||
@param tim: timer instance
|
||||
@retval 1 = PCLK1 or 2 = PCLK2
|
||||
*/
|
||||
uint8_t getTimerClkSrc(TIM_TypeDef *tim)
|
||||
{
|
||||
uint8_t clkSrc = 0;
|
||||
|
||||
if (tim != (TIM_TypeDef *)NC)
|
||||
#if defined(STM32F0xx) || defined(STM32G0xx)
|
||||
/* TIMx source CLK is PCKL1 */
|
||||
clkSrc = 1;
|
||||
|
||||
#else
|
||||
{
|
||||
/* Get source clock depending on TIM instance */
|
||||
switch ((uint32_t)tim)
|
||||
{
|
||||
#if defined(TIM2_BASE)
|
||||
|
||||
case (uint32_t)TIM2:
|
||||
#endif
|
||||
#if defined(TIM3_BASE)
|
||||
case (uint32_t)TIM3:
|
||||
#endif
|
||||
#if defined(TIM4_BASE)
|
||||
case (uint32_t)TIM4:
|
||||
#endif
|
||||
#if defined(TIM5_BASE)
|
||||
case (uint32_t)TIM5:
|
||||
#endif
|
||||
#if defined(TIM6_BASE)
|
||||
case (uint32_t)TIM6:
|
||||
#endif
|
||||
#if defined(TIM7_BASE)
|
||||
case (uint32_t)TIM7:
|
||||
#endif
|
||||
#if defined(TIM12_BASE)
|
||||
case (uint32_t)TIM12:
|
||||
#endif
|
||||
#if defined(TIM13_BASE)
|
||||
case (uint32_t)TIM13:
|
||||
#endif
|
||||
#if defined(TIM14_BASE)
|
||||
case (uint32_t)TIM14:
|
||||
#endif
|
||||
#if defined(TIM18_BASE)
|
||||
case (uint32_t)TIM18:
|
||||
#endif
|
||||
clkSrc = 1;
|
||||
break;
|
||||
#if defined(TIM1_BASE)
|
||||
|
||||
case (uint32_t)TIM1:
|
||||
#endif
|
||||
#if defined(TIM8_BASE)
|
||||
case (uint32_t)TIM8:
|
||||
#endif
|
||||
#if defined(TIM9_BASE)
|
||||
case (uint32_t)TIM9:
|
||||
#endif
|
||||
#if defined(TIM10_BASE)
|
||||
case (uint32_t)TIM10:
|
||||
#endif
|
||||
#if defined(TIM11_BASE)
|
||||
case (uint32_t)TIM11:
|
||||
#endif
|
||||
#if defined(TIM15_BASE)
|
||||
case (uint32_t)TIM15:
|
||||
#endif
|
||||
#if defined(TIM16_BASE)
|
||||
case (uint32_t)TIM16:
|
||||
#endif
|
||||
#if defined(TIM17_BASE)
|
||||
case (uint32_t)TIM17:
|
||||
#endif
|
||||
#if defined(TIM19_BASE)
|
||||
case (uint32_t)TIM19:
|
||||
#endif
|
||||
#if defined(TIM20_BASE)
|
||||
case (uint32_t)TIM20:
|
||||
#endif
|
||||
#if defined(TIM21_BASE)
|
||||
case (uint32_t)TIM21:
|
||||
#endif
|
||||
#if defined(TIM22_BASE)
|
||||
case (uint32_t)TIM22:
|
||||
#endif
|
||||
clkSrc = 2;
|
||||
break;
|
||||
|
||||
default:
|
||||
////_Error_Handler("TIM: Unknown timer instance", (int)tim);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return clkSrc;
|
||||
}
|
||||
|
||||
|
||||
#endif /* HAL_TIM_MODULE_ENABLED && !HAL_TIM_MODULE_ONLY */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
198
Gigatimer.h
Normal file
198
Gigatimer.h
Normal file
@ -0,0 +1,198 @@
|
||||
/****************************************************************************************************************************
|
||||
timer.h
|
||||
|
||||
For Portenta_H7 boards
|
||||
Written by Khoi Hoang
|
||||
|
||||
Built by Khoi Hoang https://github.com/khoih-prog/Portenta_H7_TimerInterrupt
|
||||
Licensed under MIT license
|
||||
|
||||
Now even you use all these new 16 ISR-based timers,with their maximum interval practically unlimited (limited only by
|
||||
unsigned long miliseconds), you just consume only one Portenta_H7 STM32 timer and avoid conflicting with other cores' tasks.
|
||||
The accuracy is nearly perfect compared to software timers. The most important feature is they're ISR-based timers
|
||||
Therefore, their executions are not blocked by bad-behaving functions / tasks.
|
||||
This important feature is absolutely necessary for mission-critical tasks.
|
||||
|
||||
Version: 1.4.0
|
||||
|
||||
Version Modified By Date Comments
|
||||
------- ----------- ---------- -----------
|
||||
1.2.1 K.Hoang 15/09/2021 Initial coding for Portenta_H7
|
||||
1.3.0 K.Hoang 17/09/2021 Add PWM features and examples
|
||||
1.3.1 K.Hoang 21/09/2021 Fix warnings in PWM examples
|
||||
1.4.0 K.Hoang 22/01/2022 Fix `multiple-definitions` linker error. Fix bug
|
||||
*****************************************************************************************************************************/
|
||||
|
||||
// Modified from stm32 core v2.0.0
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
Copyright (c) 2019, STMicroelectronics
|
||||
All rights reserved.
|
||||
|
||||
This software component is licensed by ST under BSD 3-Clause license,
|
||||
the "License"; You may not use this file except in compliance with the
|
||||
License. You may obtain a copy of the License at:
|
||||
opensource.org/licenses/BSD-3-Clause
|
||||
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __GIGATIMER_H
|
||||
#define __GIGATIMER_H
|
||||
#if defined(ARDUINO_GIGA)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY)
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#ifndef TIM_IRQ_PRIO
|
||||
#if (__CORTEX_M == 0x00U)
|
||||
#define TIM_IRQ_PRIO 3
|
||||
#else
|
||||
#define TIM_IRQ_PRIO 14
|
||||
#endif /* __CORTEX_M */
|
||||
|
||||
#endif /* TIM_IRQ_PRIO */
|
||||
|
||||
#ifndef TIM_IRQ_SUBPRIO
|
||||
#define TIM_IRQ_SUBPRIO 0
|
||||
#endif
|
||||
|
||||
#if defined(TIM1_BASE) && !defined(TIM1_IRQn)
|
||||
#define TIM1_IRQn TIM1_UP_IRQn
|
||||
#define TIM1_IRQHandler TIM1_UP_IRQHandler
|
||||
#endif
|
||||
|
||||
#if defined(TIM8_BASE) && !defined(TIM8_IRQn)
|
||||
#define TIM8_IRQn TIM8_UP_TIM13_IRQn
|
||||
#define TIM8_IRQHandler TIM8_UP_TIM13_IRQHandler
|
||||
#endif
|
||||
|
||||
#if defined(TIM12_BASE) && !defined(TIM12_IRQn)
|
||||
#define TIM12_IRQn TIM8_BRK_TIM12_IRQn
|
||||
#define TIM12_IRQHandler TIM8_BRK_TIM12_IRQHandler
|
||||
#endif
|
||||
|
||||
#if defined(TIM13_BASE) && !defined(TIM13_IRQn)
|
||||
#define TIM13_IRQn TIM8_UP_TIM13_IRQn
|
||||
#endif
|
||||
|
||||
#if defined(TIM14_BASE) && !defined(TIM14_IRQn)
|
||||
#define TIM14_IRQn TIM8_TRG_COM_TIM14_IRQn
|
||||
#define TIM14_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
|
||||
#endif
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
#if defined(TIM1_BASE)
|
||||
TIMER1_INDEX,
|
||||
#endif
|
||||
#if defined(TIM2_BASE)
|
||||
TIMER2_INDEX,
|
||||
#endif
|
||||
#if defined(TIM3_BASE)
|
||||
TIMER3_INDEX,
|
||||
#endif
|
||||
#if defined(TIM4_BASE)
|
||||
TIMER4_INDEX,
|
||||
#endif
|
||||
#if defined(TIM5_BASE)
|
||||
TIMER5_INDEX,
|
||||
#endif
|
||||
#if defined(TIM6_BASE)
|
||||
TIMER6_INDEX,
|
||||
#endif
|
||||
#if defined(TIM7_BASE)
|
||||
TIMER7_INDEX,
|
||||
#endif
|
||||
#if defined(TIM8_BASE)
|
||||
TIMER8_INDEX,
|
||||
#endif
|
||||
#if defined(TIM9_BASE)
|
||||
TIMER9_INDEX,
|
||||
#endif
|
||||
#if defined(TIM10_BASE)
|
||||
TIMER10_INDEX,
|
||||
#endif
|
||||
#if defined(TIM11_BASE)
|
||||
TIMER11_INDEX,
|
||||
#endif
|
||||
#if defined(TIM12_BASE)
|
||||
TIMER12_INDEX,
|
||||
#endif
|
||||
#if defined(TIM13_BASE)
|
||||
TIMER13_INDEX,
|
||||
#endif
|
||||
#if defined(TIM14_BASE)
|
||||
TIMER14_INDEX,
|
||||
#endif
|
||||
#if defined(TIM15_BASE)
|
||||
TIMER15_INDEX,
|
||||
#endif
|
||||
#if defined(TIM16_BASE)
|
||||
TIMER16_INDEX,
|
||||
#endif
|
||||
#if defined(TIM17_BASE)
|
||||
TIMER17_INDEX,
|
||||
#endif
|
||||
#if defined(TIM18_BASE)
|
||||
TIMER18_INDEX,
|
||||
#endif
|
||||
#if defined(TIM19_BASE)
|
||||
TIMER19_INDEX,
|
||||
#endif
|
||||
#if defined(TIM20_BASE)
|
||||
TIMER20_INDEX,
|
||||
#endif
|
||||
#if defined(TIM21_BASE)
|
||||
TIMER21_INDEX,
|
||||
#endif
|
||||
#if defined(TIM22_BASE)
|
||||
TIMER22_INDEX,
|
||||
#endif
|
||||
|
||||
TIMER_NUM,
|
||||
UNKNOWN_TIMER = 0XFFFF
|
||||
} timer_index_t;
|
||||
|
||||
|
||||
// This structure is used to be able to get HardwareTimer instance (C++ class)
|
||||
// from handler (C structure) specially for interrupt management
|
||||
typedef struct
|
||||
{
|
||||
// Those 2 first fields must remain in this order at the beginning of the structure
|
||||
void *__this;
|
||||
TIM_HandleTypeDef handle;
|
||||
uint32_t preemptPriority;
|
||||
uint32_t subPriority;
|
||||
} timerObj_t;
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
timerObj_t *get_timer_obj(TIM_HandleTypeDef *htim);
|
||||
|
||||
void enableTimerClock(TIM_HandleTypeDef *htim);
|
||||
void disableTimerClock(TIM_HandleTypeDef *htim);
|
||||
|
||||
uint32_t getTimerIrq(TIM_TypeDef *tim);
|
||||
uint8_t getTimerClkSrc(TIM_TypeDef *tim);
|
||||
|
||||
IRQn_Type getTimerUpIrq(TIM_TypeDef *tim);
|
||||
IRQn_Type getTimerCCIrq(TIM_TypeDef *tim);
|
||||
|
||||
#endif /* HAL_TIM_MODULE_ENABLED && !HAL_TIM_MODULE_ONLY */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
#endif /* __GIGATIMER_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
Loading…
Reference in New Issue
Block a user