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@ -75,22 +75,22 @@ void DCCTimer::startRailcomTimer(byte brakePin) {
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(there will be 7 DCC timer1 ticks in which to do this.)
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*/
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const int cutoutDuration = 436; // Desired interval in microseconds
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const int cutoutDuration = 430; // Desired interval in microseconds
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// Set up Timer2 for CTC mode (Clear Timer on Compare Match)
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TCCR2A = 0; // Clear Timer2 control register A
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TCCR2B = 0; // Clear Timer2 control register B
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TCNT2 = 0; // Initialize Timer2 counter value to 0
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// Configure Phase and Frequency Correct PWM mode
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//TCCR2A = (1 << COM2B1) | (1 << WGM20) | (1 << WGM21);
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TCCR2A = (1 << COM2B1); // enable pwm on pin 9
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TCCR2A |= (1 << WGM20);
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// Set Fast PWM mode with non-inverted output on OC2B (pin 9)
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TCCR2A = (1 << WGM21) | (1 << WGM20) | (1 << COM2B1);
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// Set Timer 2 prescaler to 32
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TCCR2B = (1 << CS21) | (1 << CS20); // 32 prescaler
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// Set the compare match value for desired interval
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OCR2A = (F_CPU / 1000000) * cutoutDuration / 32 - 1;
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OCR2A = (F_CPU / 1000000) * cutoutDuration / 64 - 1;
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// Calculate the compare match value for desired duty cycle
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OCR2B = OCR2A+1; // set duty cycle to 100%= OCR2A)
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@ -98,10 +98,23 @@ void DCCTimer::startRailcomTimer(byte brakePin) {
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// Enable Timer2 output on pin 9 (OC2B)
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DDRB |= (1 << DDB1);
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// TODO Fudge TCNT2 to sync with last tcnt1 tick + 28uS
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// Previous TIMER1 Tick was at rising end-of-packet bit
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// Cutout starts half way through first preamble
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// that is 2.5 * 58uS later.
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// TCNT1 ticks 8 times / microsecond
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// auto microsendsToFirstRailcomTick=(58+58+29)-(TCNT1/8);
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// set the railcom timer counter allowing for phase-correct
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// CHris's NOTE:
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// I dont kniow quite how this calculation works out but
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// it does seems to get a good answer.
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TCNT2=193 + (ICR1 - TCNT1)/8;
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}
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void DCCTimer::ackRailcomTimer() {
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OCR2B= 0x00; // brfake pin pwm duty cycle 0 at next tick
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OCR2B= 0x00; // brake pin pwm duty cycle 0 at next tick
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}
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