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mirror of https://github.com/DCC-EX/CommandStation-EX.git synced 2024-11-23 16:16:13 +01:00

Update for devel 5.2.20

Update for devel 5.2.20
This commit is contained in:
Ash-4 2024-01-08 17:14:56 -06:00 committed by GitHub
commit 174a456a58
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 45 additions and 23 deletions

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@ -1,5 +1,5 @@
/* /*
* © 2021-2022, Harald Barth. * © 2021-2024, Harald Barth.
* *
* This file is part of DCC-EX * This file is part of DCC-EX
* *
@ -25,6 +25,18 @@
#include "DCCWaveform.h" // for MAX_PACKET_SIZE #include "DCCWaveform.h" // for MAX_PACKET_SIZE
#include "soc/gpio_sig_map.h" #include "soc/gpio_sig_map.h"
// check for right type of ESP32
#include "soc/soc_caps.h"
#ifndef SOC_RMT_MEM_WORDS_PER_CHANNEL
#error This symobol should be defined
#endif
#if SOC_RMT_MEM_WORDS_PER_CHANNEL < 64
#warning This is not an ESP32-WROOM but some other unsupported variant
#warning You are outside of the DCC-EX supported hardware
#endif
static const byte RMT_CHAN_PER_DCC_CHAN = 2;
// Number of bits resulting out of X bytes of DCC payload data // Number of bits resulting out of X bytes of DCC payload data
// Each byte has one bit extra and at the end we have one EOF marker // Each byte has one bit extra and at the end we have one EOF marker
#define DATA_LEN(X) ((X)*9+1) #define DATA_LEN(X) ((X)*9+1)
@ -75,12 +87,30 @@ void IRAM_ATTR interrupt(rmt_channel_t channel, void *t) {
RMTChannel::RMTChannel(pinpair pins, bool isMain) { RMTChannel::RMTChannel(pinpair pins, bool isMain) {
byte ch; byte ch;
byte plen; byte plen;
// Below we check if the DCC packet actually fits into the RMT hardware
// Currently MAX_PACKET_SIZE = 5 so with checksum there are
// MAX_PACKET_SIZE+1 data packets. Each need DATA_LEN (9) bits.
// To that we add the preamble length, the fencepost DCC end bit
// and the RMT EOF marker.
// SOC_RMT_MEM_WORDS_PER_CHANNEL is either 64 (original WROOM) or
// 48 (all other ESP32 like the -C3 or -S2
// The formula to get the possible MAX_PACKET_SIZE is
//
// ALLOCATED = RMT_CHAN_PER_DCC_CHAN * SOC_RMT_MEM_WORDS_PER_CHANNEL
// MAX_PACKET_SIZE = floor((ALLOCATED - PREAMBLE_LEN - 2)/9 - 1)
//
if (isMain) { if (isMain) {
ch = 0; ch = 0;
plen = PREAMBLE_BITS_MAIN; plen = PREAMBLE_BITS_MAIN;
static_assert (DATA_LEN(MAX_PACKET_SIZE+1) + PREAMBLE_BITS_MAIN + 2 <= RMT_CHAN_PER_DCC_CHAN * SOC_RMT_MEM_WORDS_PER_CHANNEL,
"Number of DCC packet bits greater than ESP32 RMT memory available");
} else { } else {
ch = 2; ch = RMT_CHAN_PER_DCC_CHAN; // number == offset
plen = PREAMBLE_BITS_PROG; plen = PREAMBLE_BITS_PROG;
static_assert (DATA_LEN(MAX_PACKET_SIZE+1) + PREAMBLE_BITS_PROG + 2 <= RMT_CHAN_PER_DCC_CHAN * SOC_RMT_MEM_WORDS_PER_CHANNEL,
"Number of DCC packet bits greater than ESP32 RMT memory available");
} }
// preamble // preamble
@ -123,20 +153,10 @@ RMTChannel::RMTChannel(pinpair pins, bool isMain) {
config.channel = channel = (rmt_channel_t)ch; config.channel = channel = (rmt_channel_t)ch;
config.clk_div = RMT_CLOCK_DIVIDER; config.clk_div = RMT_CLOCK_DIVIDER;
config.gpio_num = (gpio_num_t)pins.pin; config.gpio_num = (gpio_num_t)pins.pin;
config.mem_block_num = 2; // With longest DCC packet 11 inc checksum (future expansion) config.mem_block_num = RMT_CHAN_PER_DCC_CHAN;
// number of bits needed is 22preamble + start + // use config
// 11*9 + extrazero + EOT = 124
// 2 mem block of 64 RMT items should be enough
ESP_ERROR_CHECK(rmt_config(&config)); ESP_ERROR_CHECK(rmt_config(&config));
addPin(pins.invpin, true); addPin(pins.invpin, true);
/*
// test: config another gpio pin
gpio_num_t gpioNum = (gpio_num_t)(pin-1);
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpioNum], PIN_FUNC_GPIO);
gpio_set_direction(gpioNum, GPIO_MODE_OUTPUT);
gpio_matrix_out(gpioNum, RMT_SIG_OUT0_IDX, 0, 0);
*/
// NOTE: ESP_INTR_FLAG_IRAM is *NOT* included in this bitmask // NOTE: ESP_INTR_FLAG_IRAM is *NOT* included in this bitmask
ESP_ERROR_CHECK(rmt_driver_install(config.channel, 0, ESP_INTR_FLAG_LOWMED|ESP_INTR_FLAG_SHARED)); ESP_ERROR_CHECK(rmt_driver_install(config.channel, 0, ESP_INTR_FLAG_LOWMED|ESP_INTR_FLAG_SHARED));

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@ -2,7 +2,7 @@
* © 2021 M Steve Todd * © 2021 M Steve Todd
* © 2021 Mike S * © 2021 Mike S
* © 2021 Fred Decker * © 2021 Fred Decker
* © 2020-2021 Harald Barth * © 2020-2024 Harald Barth
* © 2020-2021 Chris Harlow * © 2020-2021 Chris Harlow
* All rights reserved. * All rights reserved.
* *
@ -33,9 +33,9 @@
// Number of preamble bits. // Number of preamble bits.
const int PREAMBLE_BITS_MAIN = 16; const byte PREAMBLE_BITS_MAIN = 16;
const int PREAMBLE_BITS_PROG = 22; const byte PREAMBLE_BITS_PROG = 22;
const byte MAX_PACKET_SIZE = 5; // NMRA standard extended packets, payload size WITHOUT checksum. const byte MAX_PACKET_SIZE = 5; // NMRA standard extended packets, payload size WITHOUT checksum.
// The WAVE_STATE enum is deliberately numbered because a change of order would be catastrophic // The WAVE_STATE enum is deliberately numbered because a change of order would be catastrophic

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@ -85,9 +85,9 @@ EthernetInterface::EthernetInterface()
DCCTimer::getSimulatedMacAddress(mac); DCCTimer::getSimulatedMacAddress(mac);
DIAG(F("Ethernet got MAC address")); DIAG(F("Ethernet got MAC address"));
#ifdef IP_ADDRESS #ifdef IP_ADDRESS
if (Ethernet.begin(IP_ADDRESS) == 0)
#else
if (Ethernet.begin(mac, IP_ADDRESS) == 0) if (Ethernet.begin(mac, IP_ADDRESS) == 0)
#else
if (Ethernet.begin(mac) == 0)
#endif #endif
{ {
DIAG(F("Ethernet.begin FAILED")); DIAG(F("Ethernet.begin FAILED"));

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@ -1 +1 @@
#define GITHUB_SHA "devel-202401030135Z" #define GITHUB_SHA "devel-202401081219Z"

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@ -3,7 +3,9 @@
#include "StringFormatter.h" #include "StringFormatter.h"
#define VERSION "5.2.18ethCdf" #define VERSION "5.2.20ethCdf"
// 5.2.20 - Check return of Ethernet.begin()
// 5.2.19 - ESP32: Determine if the RMT hardware can handle DCC
// 5.2.18 - Display network IP fix // 5.2.18 - Display network IP fix
// 5.2.17 - ESP32 simplify network logic // 5.2.17 - ESP32 simplify network logic
// 5.2.16 - Bugfix to allow for devices using the EX-IOExpander protocol to have no analogue or no digital pins // 5.2.16 - Bugfix to allow for devices using the EX-IOExpander protocol to have no analogue or no digital pins