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Fix read operations on I2CManager for SAMD
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@ -1,6 +1,6 @@
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/*
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/*
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* © 2022 Paul M Antoine
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* © 2022 Paul M Antoine
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* © 2021, Neil McKechnie
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* © 2023, Neil McKechnie
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* All rights reserved.
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* All rights reserved.
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*
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*
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* This file is part of CommandStation-EX
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* This file is part of CommandStation-EX
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@ -107,8 +107,8 @@ void I2CManagerClass::I2C_init()
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s->I2CM.CTRLA.reg = SERCOM_I2CM_CTRLA_MODE( I2C_MASTER_OPERATION )/* |
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s->I2CM.CTRLA.reg = SERCOM_I2CM_CTRLA_MODE( I2C_MASTER_OPERATION )/* |
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SERCOM_I2CM_CTRLA_SCLSM*/ ;
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SERCOM_I2CM_CTRLA_SCLSM*/ ;
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// Enable Smart mode and Quick Command
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// Enable Smart mode (but not Quick Command)
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s->I2CM.CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN | SERCOM_I2CM_CTRLB_QCEN;
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s->I2CM.CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
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#if defined(I2C_USE_INTERRUPTS)
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#if defined(I2C_USE_INTERRUPTS)
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// Setting NVIC
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// Setting NVIC
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@ -152,18 +152,21 @@ void I2CManagerClass::I2C_sendStart() {
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bytesToReceive = currentRequest->readLen;
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bytesToReceive = currentRequest->readLen;
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// We may have initiated a stop bit before this without waiting for it.
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// We may have initiated a stop bit before this without waiting for it.
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// Wait for stop bit to be sent before sending start.
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// However, the state machine ensures that the start bit isn't sent
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while (s->I2CM.STATUS.bit.BUSSTATE == 0x2);
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// until the stop bit is complete.
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//while (s->I2CM.STATUS.bit.BUSSTATE == 0x2);
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// If anything to send, initiate write. Otherwise initiate read.
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// If anything to send, initiate write. Otherwise initiate read.
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if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
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if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
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{
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{
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// Wait while the I2C bus is BUSY
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//while (s->I2CM.STATUS.bit.BUSSTATE != 0x1);
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// Send start and address with read/write flag or'd in
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// Send start and address with read/write flag or'd in
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s->I2CM.ADDR.bit.ADDR = (currentRequest->i2cAddress << 1) | 1;
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s->I2CM.ADDR.bit.ADDR = (currentRequest->i2cAddress << 1) | 1;
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}
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}
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else {
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else {
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// Wait while the I2C bus is BUSY
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// Wait while the I2C bus is BUSY
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while (s->I2CM.STATUS.bit.BUSSTATE != 0x1);
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//while (s->I2CM.STATUS.bit.BUSSTATE != 0x1);
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s->I2CM.ADDR.bit.ADDR = (currentRequest->i2cAddress << 1ul) | 0;
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s->I2CM.ADDR.bit.ADDR = (currentRequest->i2cAddress << 1ul) | 0;
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}
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}
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}
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}
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@ -203,9 +206,6 @@ void I2CManagerClass::I2C_handleInterrupt() {
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state = I2C_STATUS_NEGATIVE_ACKNOWLEDGE;
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state = I2C_STATUS_NEGATIVE_ACKNOWLEDGE;
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} else if (bytesToSend) {
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} else if (bytesToSend) {
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// Acked, so send next byte
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// Acked, so send next byte
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if (currentRequest->operation == OPERATION_SEND_P)
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s->I2CM.DATA.bit.DATA = GETFLASH(currentRequest->writeBuffer + (txCount++));
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else
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s->I2CM.DATA.bit.DATA = currentRequest->writeBuffer[txCount++];
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s->I2CM.DATA.bit.DATA = currentRequest->writeBuffer[txCount++];
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bytesToSend--;
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bytesToSend--;
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} else if (bytesToReceive) {
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} else if (bytesToReceive) {
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@ -218,25 +218,16 @@ void I2CManagerClass::I2C_handleInterrupt() {
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}
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}
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} else if (s->I2CM.INTFLAG.bit.SB) {
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} else if (s->I2CM.INTFLAG.bit.SB) {
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// Master read completed without errors
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// Master read completed without errors
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if (bytesToReceive) {
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if (bytesToReceive == 1) {
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s->I2CM.CTRLB.bit.ACKACT = 1; // NAK final byte
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I2C_sendStop(); // send stop
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currentRequest->readBuffer[rxCount++] = s->I2CM.DATA.bit.DATA; // Store received byte
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bytesToReceive = 0;
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state = I2C_STATUS_OK; // done
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} else if (bytesToReceive) {
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s->I2CM.CTRLB.bit.ACKACT = 0; // ACK all but final byte
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currentRequest->readBuffer[rxCount++] = s->I2CM.DATA.bit.DATA; // Store received byte
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currentRequest->readBuffer[rxCount++] = s->I2CM.DATA.bit.DATA; // Store received byte
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bytesToReceive--;
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bytesToReceive--;
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} else {
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// Buffer full, issue nack/stop
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s->I2CM.CTRLB.bit.ACKACT = 1;
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I2C_sendStop();
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state = I2C_STATUS_OK;
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}
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if (bytesToReceive) {
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// PMA - I think Smart Mode means we have nothing to do...
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// More bytes to receive, issue ack and start another read
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}
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else
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{
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// Transaction finished, issue NACK and STOP.
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s->I2CM.CTRLB.bit.ACKACT = 1;
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I2C_sendStop();
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state = I2C_STATUS_OK;
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}
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}
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}
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}
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}
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}
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