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commit ec4c6b9c026e183d4c2229f042f031f4bff4a771
Author: Asbelos <asbelos@btinternet.com>
Date:   Wed Mar 5 00:30:13 2025 +0000

    Cleanup to new structure

commit 620ad6275bef8c3dd5659d913122ef579b347fef
Author: Asbelos <asbelos@btinternet.com>
Date:   Fri Feb 28 01:16:03 2025 +0000

    Railcom3
This commit is contained in:
Asbelos 2025-03-19 18:06:02 +00:00
parent 6d8ca67a2b
commit 3aa5cbcdfc
4 changed files with 101 additions and 577 deletions
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248
IO_I2CRailcom.cpp
View File

@ -38,8 +38,7 @@
* HAL(I2CRailcom, 1st vPin, vPins, I2C address)
* Parameters:
* 1st vPin : First virtual pin that EX-Rail can control to play a sound, use PLAYSOUND command (alias of ANOUT)
* vPins : Total number of virtual pins allocated (2 vPins are supported, one for each UART)
* 1st vPin for UART 0, 2nd for UART 1
* vPins : Total number of virtual pins allocated (to prevent overlaps)
* I2C Address : I2C address of the serial controller, in 0x format
*/
@ -47,43 +46,32 @@
#include "IO_I2CRailcom.h"
#include "I2CManager.h"
#include "DIAG.h"
#include "DCC.h"
#include "DCCWaveform.h"
#include "Railcom.h"
// Debug and diagnostic defines, enable too many will result in slowing the driver
#define DIAG_I2CRailcom
I2CRailcom::I2CRailcom(VPIN firstVpin, int nPins, I2CAddress i2cAddress){
I2CRailcom::I2CRailcom(VPIN firstVpin, int nPins, I2CAddress i2cAddress){
_firstVpin = firstVpin;
_nPins = nPins;
_I2CAddress = i2cAddress;
_channelMonitors[0]=new Railcom(firstVpin);
if (nPins>1) _channelMonitors[1]=new Railcom(firstVpin+1);
addDevice(this);
}
void I2CRailcom::create(VPIN firstVpin, int nPins, I2CAddress i2cAddress) {
if (nPins>2) nPins=2;
if (checkNoOverlap(firstVpin, nPins, i2cAddress))
new I2CRailcom(firstVpin, nPins, i2cAddress);
new I2CRailcom(firstVpin,nPins,i2cAddress);
}
void I2CRailcom::_begin() {
I2CManager.setClock(1000000); // TODO do we need this?
I2CManager.begin();
auto exists=I2CManager.exists(_I2CAddress);
DIAG(F("I2CRailcom: %s UART%S detected"),
DIAG(F("I2CRailcom: %s RailcomCollector %S detected"),
_I2CAddress.toString(), exists?F(""):F(" NOT"));
if (!exists) return;
_UART_CH=0;
Init_SC16IS752(); // Initialize UART0
if (_nPins>1) {
_UART_CH=1;
Init_SC16IS752(); // Initialize UART1
}
if (_deviceState==DEVSTATE_INITIALISING) _deviceState=DEVSTATE_NORMAL;
_deviceState=DEVSTATE_NORMAL;
_display();
}
@ -91,213 +79,43 @@ void I2CRailcom::create(VPIN firstVpin, int nPins, I2CAddress i2cAddress) {
void I2CRailcom::_loop(unsigned long currentMicros) {
// Read responses from device
if (_deviceState!=DEVSTATE_NORMAL) return;
// return if in cutout or cutout very soon.
if (!DCCWaveform::isRailcomSampleWindow()) return;
// IF we have 2 channels, flip channels each loop
if (_nPins>1) _UART_CH=_UART_CH?0:1;
// have we read this cutout already?
// basically we only poll once per packet when railcom cutout is working
auto cut=DCCWaveform::getRailcomCutoutCounter();
if (cutoutCounter[_UART_CH]==cut) return;
cutoutCounter[_UART_CH]=cut;
if (cutoutCounter==cut) return;
cutoutCounter=cut;
Railcom::loop(); // in case a csv read has timed out
// Read incoming raw Railcom data, and process accordingly
auto inlength = UART_ReadRegister(REG_RXLV);
if (inlength> sizeof(_inbuf)) inlength=sizeof(_inbuf);
_inbuf[0]=0;
if (inlength>0) {
// Read data buffer from UART
_outbuf[0]=(byte)(REG_RHR << 3 | _UART_CH << 1);
I2CManager.read(_I2CAddress, _inbuf, inlength, _outbuf, 1);
// Obtain data length from the collector
byte inbuf[1];
byte queryLength[]={'?'};
auto state=I2CManager.read(_I2CAddress, inbuf, 1,queryLength,sizeof(queryLength));
if (state) {
DIAG(F("RC ? state=%d"),state);
return;
}
auto length=inbuf[0];
if (length==0) return; // nothing to report
// Build a buffer and import the data from the collector
byte inbuf2[length];
byte queryData[]={'>'};
state=I2CManager.read(_I2CAddress, inbuf2, length,queryData,sizeof(queryData));
if (state) {
DIAG(F("RC > %d state=%d"),length,state);
return;
}
// HK: Reset FIFO at end of read cycle
UART_WriteRegister(REG_FCR, 0x07,false);
// Ask Railcom to interpret the raw data
_channelMonitors[_UART_CH]->process(_inbuf,inlength);
// process incoming data buffer
Railcom::process(_firstVpin,inbuf2,length);
}
void I2CRailcom::_display() {
DIAG(F("I2CRailcom: Configured on Vpins:%u-%u %S"), _firstVpin, _firstVpin+_nPins-1,
DIAG(F("I2CRailcom: %s blocks %d-%d %S"), _I2CAddress.toString(), _firstVpin, _firstVpin+_nPins-1,
(_deviceState!=DEVSTATE_NORMAL) ? F("OFFLINE") : F(""));
}
// SC16IS752 functions
// Initialise SC16IS752 only for this channel
// First a software reset
// Enable FIFO and clear TX & RX FIFO
// Need to set the following registers
// IOCONTROL set bit 1 and 2 to 0 indicating that they are GPIO
// IODIR set all bit to 1 indicating al are output
// IOSTATE set only bit 0 to 1 for UART 0, or only bit 1 for UART 1 //
// LCR bit 7=0 divisor latch (clock division registers DLH & DLL, they store 16 bit divisor),
// WORD_LEN, STOP_BIT, PARITY_ENA and PARITY_TYPE
// MCR bit 7=0 clock divisor devide-by-1 clock input
// DLH most significant part of divisor
// DLL least significant part of divisor
//
// BAUD_RATE, WORD_LEN, STOP_BIT, PARITY_ENA and PARITY_TYPE have been defined and initialized
//
// Communication parameters 8 bit, No parity, 1 stopbit
static const uint8_t WORD_LEN = 0x03; // Value LCR bit 0,1
static const uint8_t STOP_BIT = 0x00; // Value LCR bit 2
static const uint8_t PARITY_ENA = 0x00; // Value LCR bit 3
static const uint8_t PARITY_TYPE = 0x00; // Value LCR bit 4
static const uint32_t BAUD_RATE = 250000;
static const uint8_t PRESCALER = 0x01; // Value MCR bit 7
static const unsigned long SC16IS752_XTAL_FREQ_RAILCOM = 16000000; // Baud rate for Railcom signal
static const uint16_t _divisor = (SC16IS752_XTAL_FREQ_RAILCOM / PRESCALER) / (BAUD_RATE * 16);
void I2CRailcom::Init_SC16IS752(){
if (_UART_CH==0) { // HK: Currently fixed on ch 0
// only reset on channel 0}
UART_WriteRegister(REG_IOCONTROL, 0x08,false); // UART Software reset
//_deviceState=DEVSTATE_INITIALISING; // ignores error during reset which seems normal. // HK: this line is moved to below
auto iocontrol_readback = UART_ReadRegister(REG_IOCONTROL);
if (iocontrol_readback == 0x00){
_deviceState=DEVSTATE_INITIALISING;
DIAG(F("I2CRailcom: %s SRESET readback: 0x%x"),_I2CAddress.toString(), iocontrol_readback);
} else {
DIAG(F("I2CRailcom: %s SRESET: 0x%x"),_I2CAddress.toString(), iocontrol_readback);
}
}
// HK:
// You write 0x08 to the IOCONTROL register, setting bit 3 (SRESET), as per datasheet 8.18:
// "Software Reset. A write to this bit will reset the device. Once the
// device is reset this bit is automatically set to logic 0"
// So you can not readback the val you have written as this has changed.
// I've added an extra UART_ReadRegister(REG_IOCONTROL) and check if the return value is 0x00
// then set _deviceState=DEVSTATE_INITIALISING;
// HK: only do clear FIFO at end of Init_SC16IS752
//UART_WriteRegister(REG_FCR, 0x07,false); // Reset FIFO, clear RX & TX FIFO (write only)
UART_WriteRegister(REG_MCR, 0x00); // Set MCR to all 0, includes Clock divisor
//UART_WriteRegister(REG_LCR, 0x80); // Divisor latch enabled
UART_WriteRegister(REG_LCR, 0x80 | WORD_LEN | STOP_BIT | PARITY_ENA | PARITY_TYPE); // Divisor latch enabled and comm parameters set
UART_WriteRegister(REG_DLL, (uint8_t)_divisor); // Write DLL
UART_WriteRegister(REG_DLH, (uint8_t)(_divisor >> 8)); // Write DLH
auto lcr_readback = UART_ReadRegister(REG_LCR);
lcr_readback = lcr_readback & 0x7F;
UART_WriteRegister(REG_LCR, lcr_readback); // Divisor latch disabled
//UART_WriteRegister(REG_LCR, WORD_LEN | STOP_BIT | PARITY_ENA | PARITY_TYPE); // Divisor latch disabled
UART_WriteRegister(REG_FCR, 0x07,false); // Reset FIFO, clear RX & TX FIFO (write only)
#ifdef DIAG_I2CRailcom
// HK: Test to see if internal loopback works and if REG_RXLV increment to at least 0x01
// Set REG_MCR bit 4 to 1, Enable Loopback
UART_WriteRegister(REG_MCR, 0x10);
UART_WriteRegister(REG_THR, 0x88, false); // Send 0x88
auto inlen = UART_ReadRegister(REG_RXLV);
if (inlen == 0){
DIAG(F("I2CRailcom: Loopback test: %s/%d failed"),_I2CAddress.toString(), _UART_CH);
} else {
DIAG(F("Railcom: Loopback test: %s/%d RX Fifo lvl: 0x%x"),_I2CAddress.toString(), _UART_CH, inlen);
_outbuf[0]=(byte)(REG_RHR << 3 | _UART_CH << 1);
I2CManager.read(_I2CAddress, _inbuf, inlen, _outbuf, 1);
#ifdef DIAG_I2CRailcom_data
DIAG(F("Railcom: Loopback test: %s/%d RX FIFO Data"), _I2CAddress.toString(), _UART_CH);
for (int i = 0; i < inlen; i++){
DIAG(F("Railcom: Loopback data [0x%x]: 0x%x"), i, _inbuf[i]);
//DIAG(F("[0x%x]: 0x%x"), i, _inbuf[i]);
}
#endif
}
UART_WriteRegister(REG_MCR, 0x00); // Set REG_MCR back to 0x00
#endif
#ifdef DIAG_I2CRailcom
// Sent some data to check if UART baudrate is set correctly, check with logic analyzer on TX pin
UART_WriteRegister(REG_THR, 9, false);
DIAG(F("I2CRailcom: UART %s/%d Test TX = 0x09"),_I2CAddress.toString(), _UART_CH);
#endif
if (_deviceState==DEVSTATE_INITIALISING) {
DIAG(F("I2CRailcom: UART %d init complete"),_UART_CH);
}
// HK: final FIFO reset
UART_WriteRegister(REG_FCR, 0x07,false); // Reset FIFO, clear RX & TX FIFO (write only)
}
void I2CRailcom::UART_WriteRegister(uint8_t reg, uint8_t val, bool readback){
_outbuf[0] = (byte)( reg << 3 | _UART_CH << 1);
_outbuf[1]=val;
auto status=I2CManager.write(_I2CAddress, _outbuf, (uint8_t)2);
if(status!=I2C_STATUS_OK) {
DIAG(F("I2CRailcom: %s/%d write reg=0x%x,data=0x%x,I2Cstate=%d"),
_I2CAddress.toString(), _UART_CH, reg, val, status);
_deviceState=DEVSTATE_FAILED;
}
if (readback) { // Read it back to cross check
auto readback=UART_ReadRegister(reg);
if (readback!=val) {
DIAG(F("I2CRailcom readback: %s/%d reg:0x%x write=0x%x read=0x%x"),_I2CAddress.toString(),_UART_CH,reg,val,readback);
}
}
}
uint8_t I2CRailcom::UART_ReadRegister(uint8_t reg){
_outbuf[0] = (byte)(reg << 3 | _UART_CH << 1); // _outbuffer[0] has now UART_REG and UART_CH
_inbuf[0]=0;
auto status=I2CManager.read(_I2CAddress, _inbuf, 1, _outbuf, 1);
if (status!=I2C_STATUS_OK) {
DIAG(F("I2CRailcom read: %s/%d read reg=0x%x,I2Cstate=%d"),
_I2CAddress.toString(), _UART_CH, reg, status);
_deviceState=DEVSTATE_FAILED;
}
return _inbuf[0];
}
// SC16IS752 General register set (from the datasheet)
enum : uint8_t {
REG_RHR = 0x00, // FIFO Read
REG_THR = 0x00, // FIFO Write
REG_IER = 0x01, // Interrupt Enable Register R/W
REG_FCR = 0x02, // FIFO Control Register Write
REG_IIR = 0x02, // Interrupt Identification Register Read
REG_LCR = 0x03, // Line Control Register R/W
REG_MCR = 0x04, // Modem Control Register R/W
REG_LSR = 0x05, // Line Status Register Read
REG_MSR = 0x06, // Modem Status Register Read
REG_SPR = 0x07, // Scratchpad Register R/W
REG_TCR = 0x06, // Transmission Control Register R/W
REG_TLR = 0x07, // Trigger Level Register R/W
REG_TXLV = 0x08, // Transmitter FIFO Level register Read
REG_RXLV = 0x09, // Receiver FIFO Level register Read
REG_IODIR = 0x0A, // Programmable I/O pins Direction register R/W
REG_IOSTATE = 0x0B, // Programmable I/O pins State register R/W
REG_IOINTENA = 0x0C, // I/O Interrupt Enable register R/W
REG_IOCONTROL = 0x0E, // I/O Control register R/W
REG_EFCR = 0x0F, // Extra Features Control Register R/W
};
// SC16IS752 Special register set
enum : uint8_t{
REG_DLL = 0x00, // Division registers R/W
REG_DLH = 0x01, // Division registers R/W
};
// SC16IS752 Enhanced regiter set
enum : uint8_t{
REG_EFR = 0X02, // Enhanced Features Register R/W
REG_XON1 = 0x04, // R/W
REG_XON2 = 0x05, // R/W
REG_XOFF1 = 0x06, // R/W
REG_XOFF2 = 0x07, // R/W
};

109
IO_I2CRailcom.h
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@ -1,4 +1,4 @@
/*
/*
* © 2024, Henk Kruisbrink & Chris Harlow. All rights reserved.
* © 2023, Neil McKechnie. All rights reserved.
*
@ -19,47 +19,27 @@
*/
/*
*
* Dec 2023, Added NXP SC16IS752 I2C Dual UART
* The SC16IS752 has 64 bytes TX & RX FIFO buffer
* First version without interrupts from I2C UART and only RX/TX are used, interrupts may not be
* needed as the RX Fifo holds the reply
*
* Jan 2024, Issue with using both UARTs simultaniously, the secod uart seems to work but the first transmit
* corrupt data. This need more analysis and experimenatation.
* Will push this driver to the dev branch with the uart fixed to 0
* Both SC16IS750 (single uart) and SC16IS752 (dual uart, but only uart 0 is enable)
*
* myHall.cpp configuration syntax:
*
* I2CRailcom::create(1st vPin, vPins, I2C address);
*
* This polls the RailcomCollecter device once per dcc packet
* and obtains an abbreviated list of block occupancy changes which
* are fortunately very rare compared with Railcom raw data.
*
* myAutomation configuration
* HAL(I2CRailcom, 1st vPin, vPins, I2C address)
* Parameters:
* 1st vPin : First virtual pin that EX-Rail can control to play a sound, use PLAYSOUND command (alias of ANOUT)
* vPins : Total number of virtual pins allocated (2 vPins are supported, one for each UART)
* 1st vPin for UART 0, 2nd for UART 1
* I2C Address : I2C address of the serial controller, in 0x format
* vPins : Total number of virtual pins allocated
* I2C Address : I2C address of the Railcom Collector, in 0x format
*/
#ifndef IO_I2CRailcom_h
#define IO_I2CRailcom_h
#include "Arduino.h"
#include "Railcom.h"
// Debug and diagnostic defines, enable too many will result in slowing the driver
#define DIAG_I2CRailcom
#include "IODevice.h"
class I2CRailcom : public IODevice {
private:
// SC16IS752 defines
uint8_t _UART_CH=0x00; // channel 0 or 1 flips each loop if npins>1
byte _inbuf[12];
byte _outbuf[2];
byte cutoutCounter[2];
Railcom * _channelMonitors[2];
public:
byte cutoutCounter;
public:
// Constructor
I2CRailcom(VPIN firstVpin, int nPins, I2CAddress i2cAddress);
@ -72,74 +52,7 @@ public:
private:
// SC16IS752 functions
// Initialise SC16IS752 only for this channel
// First a software reset
// Enable FIFO and clear TX & RX FIFO
// Need to set the following registers
// IOCONTROL set bit 1 and 2 to 0 indicating that they are GPIO
// IODIR set all bit to 1 indicating al are output
// IOSTATE set only bit 0 to 1 for UART 0, or only bit 1 for UART 1 //
// LCR bit 7=0 divisor latch (clock division registers DLH & DLL, they store 16 bit divisor),
// WORD_LEN, STOP_BIT, PARITY_ENA and PARITY_TYPE
// MCR bit 7=0 clock divisor devide-by-1 clock input
// DLH most significant part of divisor
// DLL least significant part of divisor
//
// BAUD_RATE, WORD_LEN, STOP_BIT, PARITY_ENA and PARITY_TYPE have been defined and initialized
//
// Communication parameters 8 bit, No parity, 1 stopbit
static const uint8_t WORD_LEN = 0x03; // Value LCR bit 0,1
static const uint8_t STOP_BIT = 0x00; // Value LCR bit 2
static const uint8_t PARITY_ENA = 0x00; // Value LCR bit 3
static const uint8_t PARITY_TYPE = 0x00; // Value LCR bit 4
static const uint32_t BAUD_RATE = 250000;
static const uint8_t PRESCALER = 0x01; // Value MCR bit 7
static const unsigned long SC16IS752_XTAL_FREQ_RAILCOM = 16000000; // Baud rate for Railcom signal
static const uint16_t _divisor = (SC16IS752_XTAL_FREQ_RAILCOM / PRESCALER) / (BAUD_RATE * 16);
void Init_SC16IS752();
void UART_WriteRegister(uint8_t reg, uint8_t val, bool readback=true);
uint8_t UART_ReadRegister(uint8_t reg);
// SC16IS752 General register set (from the datasheet)
enum : uint8_t {
REG_RHR = 0x00, // FIFO Read
REG_THR = 0x00, // FIFO Write
REG_IER = 0x01, // Interrupt Enable Register R/W
REG_FCR = 0x02, // FIFO Control Register Write
REG_IIR = 0x02, // Interrupt Identification Register Read
REG_LCR = 0x03, // Line Control Register R/W
REG_MCR = 0x04, // Modem Control Register R/W
REG_LSR = 0x05, // Line Status Register Read
REG_MSR = 0x06, // Modem Status Register Read
REG_SPR = 0x07, // Scratchpad Register R/W
REG_TCR = 0x06, // Transmission Control Register R/W
REG_TLR = 0x07, // Trigger Level Register R/W
REG_TXLV = 0x08, // Transmitter FIFO Level register Read
REG_RXLV = 0x09, // Receiver FIFO Level register Read
REG_IODIR = 0x0A, // Programmable I/O pins Direction register R/W
REG_IOSTATE = 0x0B, // Programmable I/O pins State register R/W
REG_IOINTENA = 0x0C, // I/O Interrupt Enable register R/W
REG_IOCONTROL = 0x0E, // I/O Control register R/W
REG_EFCR = 0x0F, // Extra Features Control Register R/W
};
// SC16IS752 Special register set
enum : uint8_t{
REG_DLL = 0x00, // Division registers R/W
REG_DLH = 0x01, // Division registers R/W
};
// SC16IS752 Enhanced regiter set
enum : uint8_t{
REG_EFR = 0X02, // Enhanced Features Register R/W
REG_XON1 = 0x04, // R/W
REG_XON2 = 0x05, // R/W
REG_XOFF1 = 0x06, // R/W
REG_XOFF2 = 0x07, // R/W
};
};
#endif // IO_I2CRailcom_h

290
Railcom.cpp
View File

@ -1,6 +1,5 @@
/*
* SEE ADDITIONAL COPYRIGHT ATTRIBUTION BELOW
* © 2024 Chris Harlow
* © 2025 Chris Harlow
* All rights reserved.
*
* This file is part of DCC-EX
@ -19,258 +18,65 @@
* along with CommandStation. If not, see <https://www.gnu.org/licenses/>.
*/
/** Sections of this code (the decode table constants)
* are taken from openmrn
* https://github.com/bakerstu/openmrn/blob/master/src/dcc/RailCom.cxx
* under the following copyright.
*
* Copyright (c) 2014, Balazs Racz
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
**/
#include "Railcom.h"
#include "defines.h"
#include "FSH.h"
#include "DCC.h"
#include "DIAG.h"
#include "DCCWaveform.h"
/** Table for 8-to-6 decoding of railcom data. This table can be indexed by the
* 8-bit value read from the railcom channel, and the return value will be
* either a 6-bit number, or one of the defined Railcom constrantrs. If the
* value is invalid, the INV constant is returned. */
// These values appear in the railcom_decode table to mean special symbols.
static constexpr uint8_t
// highest valid 6-bit value
MAX_VALID = 0x3F,
/// invalid value (not conforming to the 4bit weighting requirement)
INV = 0xff,
/// Railcom ACK; the decoder received the message ok. NOTE: There are
/// two codepoints that map to this.
ACK = 0xfe,
/// The decoder rejected the packet.
NACK = 0xfd,
/// The decoder is busy; send the packet again. This is typically
/// returned when a POM CV write is still pending; the caller must
/// re-try sending the packet later.
RCBUSY = 0xfc,
/// Reserved for future expansion.
RESVD1 = 0xfb,
/// Reserved for future expansion.
RESVD2 = 0xfa;
const uint8_t HIGHFLASH decode[256] =
// 0|8 1|9 2|a 3|b 4|c 5|d 6|e 7|f
{ INV, INV, INV, INV, INV, INV, INV, INV, // 0
INV, INV, INV, INV, INV, INV, INV, ACK, // 0
INV, INV, INV, INV, INV, INV, INV, 0x33, // 1
INV, INV, INV, 0x34, INV, 0x35, 0x36, INV, // 1
INV, INV, INV, INV, INV, INV, INV, 0x3A, // 2
INV, INV, INV, 0x3B, INV, 0x3C, 0x37, INV, // 2
INV, INV, INV, 0x3F, INV, 0x3D, 0x38, INV, // 3
INV, 0x3E, 0x39, INV, NACK, INV, INV, INV, // 3
INV, INV, INV, INV, INV, INV, INV, 0x24, // 4
INV, INV, INV, 0x23, INV, 0x22, 0x21, INV, // 4
INV, INV, INV, 0x1F, INV, 0x1E, 0x20, INV, // 5
INV, 0x1D, 0x1C, INV, 0x1B, INV, INV, INV, // 5
INV, INV, INV, 0x19, INV, 0x18, 0x1A, INV, // 6
INV, 0x17, 0x16, INV, 0x15, INV, INV, INV, // 6
INV, 0x25, 0x14, INV, 0x13, INV, INV, INV, // 7
0x32, INV, INV, INV, INV, INV, INV, INV, // 7
INV, INV, INV, INV, INV, INV, INV, RESVD2, // 8
INV, INV, INV, 0x0E, INV, 0x0D, 0x0C, INV, // 8
INV, INV, INV, 0x0A, INV, 0x09, 0x0B, INV, // 9
INV, 0x08, 0x07, INV, 0x06, INV, INV, INV, // 9
INV, INV, INV, 0x04, INV, 0x03, 0x05, INV, // a
INV, 0x02, 0x01, INV, 0x00, INV, INV, INV, // a
INV, 0x0F, 0x10, INV, 0x11, INV, INV, INV, // b
0x12, INV, INV, INV, INV, INV, INV, INV, // b
INV, INV, INV, RESVD1, INV, 0x2B, 0x30, INV, // c
INV, 0x2A, 0x2F, INV, 0x31, INV, INV, INV, // c
INV, 0x29, 0x2E, INV, 0x2D, INV, INV, INV, // d
0x2C, INV, INV, INV, INV, INV, INV, INV, // d
INV, RCBUSY, 0x28, INV, 0x27, INV, INV, INV, // e
0x26, INV, INV, INV, INV, INV, INV, INV, // e
ACK, INV, INV, INV, INV, INV, INV, INV, // f
INV, INV, INV, INV, INV, INV, INV, INV, // f
};
/// Packet identifiers from Mobile Decoders.
enum RailcomMobilePacketId
{
RMOB_POM = 0,
RMOB_ADRHIGH = 1,
RMOB_ADRLOW = 2,
RMOB_EXT = 3,
RMOB_DYN = 7,
RMOB_XPOM0 = 8,
RMOB_XPOM1 = 9,
RMOB_XPOM2 = 10,
RMOB_XPOM3 = 11,
RMOB_SUBID = 12,
RMOB_LOGON_ASSIGN_FEEDBACK = 13,
RMOB_LOGON_ENABLE_FEEDBACK = 15,
};
// each railcom block is represented by an instance of this class.
// The blockvpin is the vpin associated with this block for the purposes of
// a HAL driver for the railcom detection and the EXRAIL ONBLOCKENTER/ONBLOCKEXIT
// need to know if there is any detector Railcom detector
// otherwise <r cab cv> would block the async reply feature.
bool Railcom::hasActiveDetectors=false;
Railcom::Railcom(uint16_t blockvpin) {
DIAG(F("Create Railcom block %d"),blockvpin);
haveHigh=false;
haveLow=false;
packetsWithNoData=0;
lastChannel1Loco=0;
vpin=blockvpin;
}
uint16_t Railcom::expectLoco=0;
uint16_t Railcom::expectCV=0;
unsigned long Railcom::expectWait=0;
ACK_CALLBACK Railcom::expectCallback=0;
// Process is called by a raw data collector.
void Railcom::process(uint8_t * inbound, uint8_t length) {
hasActiveDetectors=true;
if (length<2 || (inbound[0]==0 && inbound[1]==0)) {
noData();
return;
}
if (Diag::RAILCOM) {
static const char hexchars[]="0123456789ABCDEF";
if (length>2) {
USB_SERIAL.print(F("<*R "));
for (byte i=0;i<length;i++) {
if (i==2) Serial.write(' ');
USB_SERIAL.write(hexchars[inbound[i]>>4]);
USB_SERIAL.write(hexchars[inbound[i]& 0x0F ]);
}
USB_SERIAL.print(F(" *>\n"));
}
}
if (expectCV && DCCWaveform::getRailcomLastLocoAddress()==expectLoco) {
if (length>=4) {
auto v2=GETHIGHFLASH(decode,inbound[2]);
auto v3=GETHIGHFLASH(decode,inbound[3]);
uint16_t packet=(v2<<6) | (v3 & 0x3f);
// packet is 12 bits TTTTDDDDDDDD
byte type=(packet>>8) & 0x0F;
byte data= packet & 0xFF;
if (type==RMOB_POM) {
// DIAG(F("POM READ loco=%d cv(%d)=%d/0x%x"), expectLoco, expectCV,data,data);
expectCallback(data);
expectCV=0;
}
}
}
if (expectCV && (millis()-expectWait)> POM_READ_TIMEOUT) { // still waiting
expectCallback(-1);
expectCV=0;
}
auto v1=GETHIGHFLASH(decode,inbound[0]);
auto v2=(length>1) ? GETHIGHFLASH(decode,inbound[1]):INV;
uint16_t packet=(v1<<6) | (v2 & 0x3f);
// packet is 12 bits TTTTDDDDDDDD
byte type=(packet>>8) & 0x0F;
byte data= packet & 0xFF;
if (type==RMOB_ADRHIGH) {
holdoverHigh=data;
haveHigh=true;
packetsWithNoData=0;
}
else if (type==RMOB_ADRLOW) {
holdoverLow=data;
haveLow=true;
packetsWithNoData=0;
}
else {
// channel1 is unreadable or not loco address so maybe multiple locos in block
if (length>2 && GETHIGHFLASH(decode,inbound[0])!=INV) {
// it looks like we have channel2 data
auto thisLoco=DCCWaveform::getRailcomLastLocoAddress();
if (Diag::RAILCOM) DIAG(F("c2=%d"),thisLoco);
if (thisLoco==lastChannel1Loco) return;
if (thisLoco) DCC::setLocoInBlock(thisLoco,vpin,false); // this loco is in block, but not exclusive
return;
}
// channel1 no good and no channel2
noData();
return;
}
if (haveHigh && haveLow) {
uint16_t thisLoco=((holdoverHigh<<8)| holdoverLow) & 0x7FFF; // drop top bit
if (thisLoco!=lastChannel1Loco) {
// the exclusive DCC call is quite expensive, we dont want to call it every packet
if (Diag::RAILCOM) DIAG(F("h=%x l=%xc1=%d"),holdoverHigh, holdoverLow,thisLoco);
DCC::setLocoInBlock(thisLoco,vpin,true); // only this loco is in block
lastChannel1Loco=thisLoco;
}
}
}
void Railcom::noData() {
if (packetsWithNoData>MAX_WAIT_FOR_GLITCH) return;
if (packetsWithNoData==MAX_WAIT_FOR_GLITCH) {
// treat as no loco
haveHigh=false;
haveLow=false;
lastChannel1Loco=0;
// Previous locos (if any) is exiting block
DCC::clearBlock(vpin);
}
packetsWithNoData++;
}
// anticipate is used when waiting for a CV read from a railcom loco
void Railcom::anticipate(uint16_t loco, uint16_t cv, ACK_CALLBACK callback) {
if (!hasActiveDetectors) {
// if there are no active railcom detectors, this will
// not be timed out in process()... so deny it now.
callback(-2);
return;
}
expectLoco=loco;
expectCV=cv;
expectWait=millis(); // start of timeout
expectCallback=callback;
};
}
// process is called to handle data buffer sent by collector
void Railcom::process(int16_t firstVpin,byte * buffer, byte length) {
// block,locohi,locolow
// block|0x80,data pom read cv
byte i=0;
while (i<length) {
byte block=buffer[i] & 0x3f;
byte type=buffer[i]>>6;
switch (type) {
// a type=0 record has block,locohi,locolow
case 0: {
uint16_t locoid= ((uint16_t)buffer[i+1])<<8 | ((uint16_t)buffer[i+2]);
DIAG(F("RC3 b=%d l=%d"),block,locoid);
if (locoid==0) DCC::clearBlock(firstVpin+block);
else DCC::setLocoInBlock(locoid,firstVpin+block,true);
i+=3;
}
break;
case 2: { // csv value from POM read
byte value=buffer[i+1];
if (expectCV && DCCWaveform::getRailcomLastLocoAddress()==expectLoco) {
DCC::setLocoInBlock(expectLoco,firstVpin+block,false);
if (expectCallback) expectCallback(value);
expectCV=0;
}
i+=2;
}
break;
default:
DIAG(F("Unknown RC Collector code %d"),type);
return;
}
}
}
// loop() is called to detect timeouts waiting for a POM read result
void Railcom::loop() {
if (expectCV && (millis()-expectWait)> POM_READ_TIMEOUT) { // still waiting
expectCallback(-1);
expectCV=0;
}
}

31
Railcom.h
View File

@ -1,5 +1,5 @@
/*
* © 2024 Chris Harlow
* © 202 5Chris Harlow
* All rights reserved.
*
* This file is part of DCC-EX
@ -26,28 +26,15 @@ typedef void (*ACK_CALLBACK)(int16_t result);
class Railcom {
public:
Railcom(uint16_t vpin);
/* Process returns -1: Call again next packet
0: No loco on track
>0: loco id
*/
void process(uint8_t * inbound,uint8_t length);
static void anticipate(uint16_t loco, uint16_t cv, ACK_CALLBACK callback);
static void anticipate(uint16_t loco, uint16_t cv, ACK_CALLBACK callback);
static void process(int16_t firstVpin,byte * buffer, byte length );
static void loop();
private:
static bool hasActiveDetectors;
static const unsigned long POM_READ_TIMEOUT=500; // as per spec
static uint16_t expectCV,expectLoco;
static unsigned long expectWait;
static ACK_CALLBACK expectCallback;
void noData();
uint16_t vpin;
uint8_t holdoverHigh,holdoverLow;
bool haveHigh,haveLow;
uint8_t packetsWithNoData;
uint16_t lastChannel1Loco;
static const byte MAX_WAIT_FOR_GLITCH=20; // number of dead or empty packets before assuming loco=0
static const unsigned long POM_READ_TIMEOUT=500; // as per spec
static uint16_t expectCV,expectLoco;
static unsigned long expectWait;
static ACK_CALLBACK expectCallback;
static const byte MAX_WAIT_FOR_GLITCH=20; // number of dead or empty packets before assuming loco=0
};
#endif