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https://github.com/DCC-EX/CommandStation-EX.git
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Update I2CManager_STM32.h
Remove debug code (writing to pin D2). Update comments. Restructure.
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4f56837d28
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@ -238,6 +238,8 @@ void I2CManagerClass::I2C_sendStart() {
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// and the STOP bit is already set, we could output multiple STOP conditions.
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while (s->CR1 & I2C_CR1_STOP) {} // Wait for STOP bit to reset
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s->CR2 |= (I2C_CR2_ITEVTEN | I2C_CR2_ITERREN); // Enable interrupts
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s->CR2 &= ~I2C_CR2_ITBUFEN; // Don't enable buffer interupts yet.
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s->CR1 &= ~I2C_CR1_POS; // Clear the POS bit
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s->CR1 |= (I2C_CR1_ACK | I2C_CR1_START); // Enable the ACK and generate START
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transactionState = TS_START;
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@ -248,7 +250,6 @@ void I2CManagerClass::I2C_sendStart() {
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***************************************************************************/
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void I2CManagerClass::I2C_sendStop() {
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s->CR1 |= I2C_CR1_STOP; // Stop I2C
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//while (s->CR1 & I2C_CR1_STOP) {} // Wait for STOP bit to reset
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}
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/***************************************************************************
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@ -261,7 +262,7 @@ void I2CManagerClass::I2C_close() {
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// Should never happen, but wait for up to 500us only.
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unsigned long startTime = micros();
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while ((s->CR1 & I2C_CR1_PE) != 0) {
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if (micros() - startTime >= 500UL) break;
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if ((int32_t)(micros() - startTime) >= 500) break;
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}
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NVIC_DisableIRQ(I2C1_EV_IRQn);
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NVIC_DisableIRQ(I2C1_ER_IRQn);
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@ -275,9 +276,6 @@ void I2CManagerClass::I2C_close() {
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void I2CManagerClass::I2C_handleInterrupt() {
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volatile uint16_t temp_sr1, temp_sr2;
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pinMode(D2, OUTPUT);
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digitalWrite(D2, 1);
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temp_sr1 = s->SR1;
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// Check for errors first
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@ -330,8 +328,8 @@ void I2CManagerClass::I2C_handleInterrupt() {
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break;
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case TS_W_ADDR:
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temp_sr2 = s->SR2; // read SR2 to complete clearing the ADDR bit
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if (temp_sr1 & I2C_SR1_ADDR) {
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temp_sr2 = s->SR2; // read SR2 to complete clearing the ADDR bit
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// Event EV6
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// Address sent successfully, device has ack'd in response.
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if (!bytesToSend) {
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@ -340,60 +338,65 @@ void I2CManagerClass::I2C_handleInterrupt() {
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completionStatus = I2C_STATUS_OK;
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state = I2C_STATE_COMPLETED;
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} else {
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if (bytesToSend <= 2) {
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// After this interrupt, we will have no more data to send.
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// Next event of interest will be the BTF interrupt, so disable TXE interrupt
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s->CR2 &= ~I2C_CR2_ITBUFEN;
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transactionState = TS_W_STOP;
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} else {
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// More data to send, enable TXE interrupt.
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s->CR2 |= I2C_CR2_ITBUFEN;
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transactionState = TS_W_DATA;
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}
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// Put one or two bytes into DR to avoid interrupts
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// Put one byte into DR to load shift register.
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s->DR = sendBuffer[txCount++];
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bytesToSend--;
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if (bytesToSend) {
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// Put another byte to load DR
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s->DR = sendBuffer[txCount++];
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bytesToSend--;
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}
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if (!bytesToSend) {
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// No more bytes to send.
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// The TXE interrupt occurs when the DR is empty, and the BTF interrupt
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// occurs when the shift register is also empty (one character later).
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// To avoid repeated TXE interrupts during this time, we disable TXE interrupt.
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s->CR2 &= ~I2C_CR2_ITBUFEN; // Wait for BTF interrupt, disable TXE interrupt
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transactionState = TS_W_STOP;
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} else {
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// More data remaining to send after this interrupt, enable TXE interrupt.
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s->CR2 |= I2C_CR2_ITBUFEN;
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transactionState = TS_W_DATA;
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}
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}
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}
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break;
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case TS_W_DATA:
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if (temp_sr1 & I2C_SR1_TXE) {
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// Event EV8_1/EV8/EV8_2
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// Event EV8_1/EV8
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// Transmitter empty, write a byte to it.
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if (bytesToSend) {
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if (bytesToSend == 1) {
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// We will next need to wait for BTF.
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// TXE becomes set one byte before BTF is set, so disable
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// TXE interrupt while we're waiting for BTF, to suppress
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// repeated interrupts during that period.
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s->CR2 &= ~I2C_CR2_ITBUFEN;
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transactionState = TS_W_STOP;
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}
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s->DR = sendBuffer[txCount++];
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bytesToSend--;
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if (!bytesToSend) {
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s->CR2 &= ~I2C_CR2_ITBUFEN; // Disable TXE interrupt
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transactionState = TS_W_STOP;
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}
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}
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}
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}
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break;
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case TS_W_STOP:
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if ((temp_sr1 & I2C_SR1_BTF) && (temp_sr1 & I2C_SR1_TXE)) {
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if (temp_sr1 & I2C_SR1_BTF) {
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// Event EV8_2
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// All writes finished.
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// Done, last character sent. Anything to receive?
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if (bytesToReceive) {
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// Start a read operation by sending (re)start
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I2C_sendStart();
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I2C_sendStart();
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// NOTE: Three redundant BTF interrupts take place between the
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// first BTF interrupt and the START interrupt. I've tried all sorts
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// of ways to eliminate them, and the only thing that worked for
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// me was to loop until the BTF bit becomes reset. Either way,
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// it's a waste of processor time. Anyone got a solution?
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//while (s->SR1 && I2C_SR1_BTF) {}
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transactionState = TS_START;
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} else {
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// Done.
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I2C_sendStop();
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transactionState = TS_IDLE;
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completionStatus = I2C_STATUS_OK;
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state = I2C_STATE_COMPLETED;
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}
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s->SR1 &= I2C_SR1_BTF; // Clear BTF interrupt
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}
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break;
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@ -477,9 +480,11 @@ void I2CManagerClass::I2C_handleInterrupt() {
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}
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break;
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}
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// If we've received an interrupt at any other time, we're not interested so clear it
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// to prevent it recurring ad infinitum.
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s->SR1 = 0;
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}
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delayMicroseconds(1);
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digitalWrite(D2, 0);
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}
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#endif /* I2CMANAGER_STM32_H */
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