diff --git a/DCCRMT.h b/DCCRMT.h index 33257a0..3a20027 100644 --- a/DCCRMT.h +++ b/DCCRMT.h @@ -44,6 +44,12 @@ class RMTChannel { return true; return dataReady; }; + inline void waitForDataCopy() { + while(1) { // do nothing and wait for interrupt clearing dataReady to happen + if (dataReady == false) + break; + } + }; inline uint32_t packetCount() { return packetCounter; }; private: diff --git a/DCCWaveformRMT.cpp b/DCCWaveformRMT.cpp index aa3c223..4c10ceb 100644 --- a/DCCWaveformRMT.cpp +++ b/DCCWaveformRMT.cpp @@ -70,7 +70,11 @@ void DCCWaveform::begin() { void DCCWaveform::schedulePacket(const byte buffer[], byte byteCount, byte repeats) { if (byteCount > MAX_PACKET_SIZE) return; // allow for chksum + RMTChannel *rmtchannel = (isMainTrack ? rmtMainChannel : rmtProgChannel); + if (rmtchannel == NULL) + return; // no idea to prepare packet if we can not send it anyway + rmtchannel->waitForDataCopy(); // blocking wait so we can write into buffer byte checksum = 0; for (byte b = 0; b < byteCount; b++) { checksum ^= buffer[b]; @@ -88,13 +92,7 @@ void DCCWaveform::schedulePacket(const byte buffer[], byte byteCount, byte repea { int ret = 0; do { - if(isMainTrack) { - if (rmtMainChannel != NULL) - ret = rmtMainChannel->RMTfillData(pendingPacket, pendingLength, pendingRepeats); - } else { - if (rmtProgChannel != NULL) - ret = rmtProgChannel->RMTfillData(pendingPacket, pendingLength, pendingRepeats); - } + ret = rmtchannel->RMTfillData(pendingPacket, pendingLength, pendingRepeats); } while(ret > 0); } } diff --git a/GITHUB_SHA.h b/GITHUB_SHA.h index 1024a4f..b1c3d8f 100644 --- a/GITHUB_SHA.h +++ b/GITHUB_SHA.h @@ -1 +1 @@ -#define GITHUB_SHA "devel-202501092043Z" +#define GITHUB_SHA "devel-202501171827Z" diff --git a/version.h b/version.h index b15e3d2..2ba389b 100644 --- a/version.h +++ b/version.h @@ -3,7 +3,8 @@ #include "StringFormatter.h" -#define VERSION "5.5.6" +#define VERSION "5.5.7" +// 5.5.7 - ESP32 bugfix packet buffer race (as 5.4.1) // 5.5.6 - Fix ESP32 build bug caused by include reference loop // 5.5.5 - Railcom implementation with IO_I2CRailcom driver // - response analysis and block management.