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Railcom timing
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@ -57,66 +57,59 @@ void DCCTimer::begin(INTERRUPT_CALLBACK callback) {
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TCCR1B = _BV(WGM13) | _BV(CS10); // Mode 8, clock select 1
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TIMSK1 = _BV(TOIE1); // Enable Software interrupt
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interrupts();
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//diagnostic pinMode(4,OUTPUT);
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}
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void DCCTimer::startRailcomTimer(byte brakePin) {
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(void) brakePin; // Ignored... works on pin 9 only
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// diagnostic digitalWrite(4,HIGH);
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/* The Railcom timer is started in such a way that it
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- First triggers 28uS after the last TIMER1 tick.
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- First triggers 58+29 uS after the previous TIMER1 tick.
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This provides an accurate offset (in High Accuracy mode)
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for the start of the Railcom cutout.
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- Sets the Railcom pin high at first tick,
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because its been setup with 100% PWM duty cycle.
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- Sets the Railcom pin high at first tick and subsequent ticks
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until its reset to setting pin 9 low at next tick.
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- Cycles at 436uS so the second tick is the
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correct distance from the cutout.
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- Waveform code is responsible for altering the PWM
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duty cycle to 0% any time between the first and last tick.
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- Waveform code is responsible for resetting
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any time between the first and second tick.
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(there will be 7 DCC timer1 ticks in which to do this.)
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*/
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(void) brakePin; // Ignored... works on pin 9 only
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const int cutoutDuration = 430; // Desired interval in microseconds
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// Set up Timer2 for CTC mode (Clear Timer on Compare Match)
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TCCR2A = 0; // Clear Timer2 control register A
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TCCR2B = 0; // Clear Timer2 control register B
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TCNT2 = 0; // Initialize Timer2 counter value to 0
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// Configure Phase and Frequency Correct PWM mode
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TCCR2A = (1 << COM2B1); // enable pwm on pin 9
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TCCR2A |= (1 << WGM20);
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const int cycle=cutoutDuration/2;
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// Set Timer 2 prescaler to 32
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TCCR2B = (1 << CS21) | (1 << CS20); // 32 prescaler
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// Set the compare match value for desired interval
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OCR2A = (F_CPU / 1000000) * cutoutDuration / 64 - 1;
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// Calculate the compare match value for desired duty cycle
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OCR2B = OCR2A+1; // set duty cycle to 100%= OCR2A)
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const byte RailcomFudge0=58+58+29;
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// Set Timer2 to CTC mode with set on compare match
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TCCR2A = (1 << WGM21) | (1 << COM2B0) | (1 << COM2B1);
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// Prescaler of 32
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TCCR2B = (1 << CS21) | (1 << CS20);
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OCR2A = cycle-1; // Compare match value for 430 uS
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// Enable Timer2 output on pin 9 (OC2B)
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DDRB |= (1 << DDB1);
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// TODO Fudge TCNT2 to sync with last tcnt1 tick + 28uS
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// RailcomFudge2 is the expected time from idealised
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// setup call (at previous DCC timer interrupt) to the cutout.
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// This value should be reduced to reflect the Timer1 value
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// measuring the time since the previous hardware interrupt
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byte tcfudge=TCNT1/16;
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TCNT2=cycle-RailcomFudge0/2+tcfudge/2;
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// Previous TIMER1 Tick was at rising end-of-packet bit
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// Cutout starts half way through first preamble
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// that is 2.5 * 58uS later.
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// TCNT1 ticks 8 times / microsecond
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// auto microsendsToFirstRailcomTick=(58+58+29)-(TCNT1/8);
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// set the railcom timer counter allowing for phase-correct
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// CHris's NOTE:
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// I dont kniow quite how this calculation works out but
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// it does seems to get a good answer.
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TCNT2=193 + (ICR1 - TCNT1)/8;
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}
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}
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void DCCTimer::ackRailcomTimer() {
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OCR2B= 0x00; // brake pin pwm duty cycle 0 at next tick
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// Change Timer2 to CTC mode with RESET pin 9 on next compare match
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TCCR2A = (1 << WGM21) | (1 << COM2B1);
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// diagnostic digitalWrite(4,LOW);
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}
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@ -31,7 +31,7 @@
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#include "DCCACK.h"
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#include "DIAG.h"
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bool DCCWaveform::cutoutNextTime=false;
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DCCWaveform DCCWaveform::mainTrack(PREAMBLE_BITS_MAIN, true);
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DCCWaveform DCCWaveform::progTrack(PREAMBLE_BITS_PROG, false);
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@ -71,9 +71,14 @@ void DCCWaveform::loop() {
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#pragma GCC push_options
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#pragma GCC optimize ("-O3")
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void DCCWaveform::interruptHandler() {
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// call the timer edge sensitive actions for progtrack and maintrack
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// member functions would be cleaner but have more overhead
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if (cutoutNextTime) {
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cutoutNextTime=false;
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DCCTimer::startRailcomTimer(9);
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}
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byte sigMain=signalTransform[mainTrack.state];
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byte sigProg=TrackManager::progTrackSyncMain? sigMain : signalTransform[progTrack.state];
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@ -140,6 +145,12 @@ void DCCWaveform::interrupt2() {
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// or WAVE_HIGH_0 for a 0 bit.
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if (remainingPreambles > 0 ) {
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state=WAVE_MID_1; // switch state to trigger LOW on next interrupt
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// predict railcom cutout on next interrupt
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cutoutNextTime= remainingPreambles==requiredPreambles
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&& railcomActive
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&& isMainTrack;
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remainingPreambles--;
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// As we get to the end of the preambles, open the reminder window.
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@ -147,7 +158,7 @@ void DCCWaveform::interrupt2() {
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// that the reminder doesn't block a more urgent packet.
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reminderWindowOpen=transmitRepeats==0 && remainingPreambles<4 && remainingPreambles>1;
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if (remainingPreambles==1) promotePendingPacket();
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else if (remainingPreambles==10 && isMainTrack && railcomActive) DCCTimer::ackRailcomTimer();
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else if (remainingPreambles==14 && isMainTrack && railcomActive) DCCTimer::ackRailcomTimer();
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// Update free memory diagnostic as we don't have anything else to do this time.
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// Allow for checkAck and its called functions using 22 bytes more.
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else DCCTimer::updateMinimumFreeMemoryISR(22);
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@ -171,13 +182,7 @@ void DCCWaveform::interrupt2() {
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bytes_sent = 0;
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// preamble for next packet will start...
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remainingPreambles = requiredPreambles;
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// set the railcom coundown to trigger half way
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// through the first preamble bit.
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// Note.. we are still sending the last packet bit
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// and we then have to allow for the packet end bit
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if (isMainTrack && railcomActive) DCCTimer::startRailcomTimer(9);
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}
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}
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}
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}
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#pragma GCC pop_options
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@ -114,7 +114,7 @@ class DCCWaveform {
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byte pendingRepeats;
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static volatile bool railcomActive; // switched on by user
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static volatile bool railcomDebug; // switched on by user
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static bool cutoutNextTime; // railcom
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#ifdef ARDUINO_ARCH_ESP32
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static RMTChannel *rmtMainChannel;
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static RMTChannel *rmtProgChannel;
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