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https://github.com/DCC-EX/CommandStation-EX.git
synced 2024-11-30 03:26:13 +01:00
Merge branch 'devel_railcom_Mega' into devel
This commit is contained in:
commit
6f1df6ce8e
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@ -1035,7 +1035,30 @@ bool DCCEXParser::parseC(Print *stream, int16_t params, int16_t p[]) {
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DCC::setGlobalSpeedsteps(128);
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DIAG(F("128 Speedsteps"));
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return true;
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case "RAILCOM"_hk:
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{ // <C RAILCOM ON|OFF|DEBUG >
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if (params<2) return false;
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bool on=false;
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bool debug=false;
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switch (p[1]) {
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case "ON"_hk:
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case 1:
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on=true;
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break;
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case "DEBUG"_hk:
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on=true;
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debug=true;
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break;
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case "OFF"_hk:
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case 0:
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break;
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default:
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return false;
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}
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DIAG(F("Railcom %S")
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,DCCWaveform::setRailcom(on,debug)?F("ON"):F("OFF"));
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return true;
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}
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#ifndef DISABLE_PROG
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case "ACK"_hk: // <D ACK ON/OFF> <D ACK [LIMIT|MIN|MAX|RETRY] Value>
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if (params >= 3) {
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@ -62,6 +62,8 @@ class DCCTimer {
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static bool isPWMPin(byte pin);
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static void setPWM(byte pin, bool high);
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static void clearPWM();
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static void startRailcomTimer(byte brakePin);
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static void ackRailcomTimer();
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static void DCCEXanalogWriteFrequency(uint8_t pin, uint32_t frequency);
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static void DCCEXanalogWrite(uint8_t pin, int value);
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@ -39,6 +39,9 @@ INTERRUPT_CALLBACK interruptHandler=0;
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#define TIMER1_A_PIN 11
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#define TIMER1_B_PIN 12
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#define TIMER1_C_PIN 13
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#define TIMER2_A_PIN 10
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#define TIMER2_B_PIN 9
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#else
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#define TIMER1_A_PIN 9
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#define TIMER1_B_PIN 10
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@ -55,6 +58,66 @@ void DCCTimer::begin(INTERRUPT_CALLBACK callback) {
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interrupts();
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}
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void DCCTimer::startRailcomTimer(byte brakePin) {
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/* The Railcom timer is started in such a way that it
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- First triggers 28uS after the last TIMER1 tick.
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This provides an accurate offset (in High Accuracy mode)
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for the start of the Railcom cutout.
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- Sets the Railcom pin high at first tick,
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because its been setup with 100% PWM duty cycle.
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- Cycles at 436uS so the second tick is the
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correct distance from the cutout.
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- Waveform code is responsible for altering the PWM
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duty cycle to 0% any time between the first and last tick.
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(there will be 7 DCC timer1 ticks in which to do this.)
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*/
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const int cutoutDuration = 430; // Desired interval in microseconds
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// Set up Timer2 for CTC mode (Clear Timer on Compare Match)
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TCCR2A = 0; // Clear Timer2 control register A
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TCCR2B = 0; // Clear Timer2 control register B
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TCNT2 = 0; // Initialize Timer2 counter value to 0
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// Configure Phase and Frequency Correct PWM mode
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TCCR2A = (1 << COM2B1); // enable pwm on pin 9
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TCCR2A |= (1 << WGM20);
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// Set Timer 2 prescaler to 32
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TCCR2B = (1 << CS21) | (1 << CS20); // 32 prescaler
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// Set the compare match value for desired interval
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OCR2A = (F_CPU / 1000000) * cutoutDuration / 64 - 1;
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// Calculate the compare match value for desired duty cycle
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OCR2B = OCR2A+1; // set duty cycle to 100%= OCR2A)
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// Enable Timer2 output on pin 9 (OC2B)
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DDRB |= (1 << DDB1);
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// TODO Fudge TCNT2 to sync with last tcnt1 tick + 28uS
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// Previous TIMER1 Tick was at rising end-of-packet bit
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// Cutout starts half way through first preamble
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// that is 2.5 * 58uS later.
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// TCNT1 ticks 8 times / microsecond
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// auto microsendsToFirstRailcomTick=(58+58+29)-(TCNT1/8);
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// set the railcom timer counter allowing for phase-correct
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// CHris's NOTE:
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// I dont kniow quite how this calculation works out but
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// it does seems to get a good answer.
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TCNT2=193 + (ICR1 - TCNT1)/8;
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}
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void DCCTimer::ackRailcomTimer() {
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OCR2B= 0x00; // brake pin pwm duty cycle 0 at next tick
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}
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// ISR called by timer interrupt every 58uS
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ISR(TIMER1_OVF_vect){ interruptHandler(); }
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@ -80,6 +80,14 @@ extern char *__malloc_heap_start;
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interruptHandler();
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}
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void DCCTimer::startRailcomTimer(byte brakePin) {
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// TODO: for intended operation see DCCTimerAVR.cpp
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}
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void DCCTimer::ackRailcomTimer() {
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// TODO: for intended operation see DCCTimerAVR.cpp
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}
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bool DCCTimer::isPWMPin(byte pin) {
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(void) pin;
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return false; // TODO what are the relevant pins?
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@ -76,6 +76,14 @@ void DCCTimer::begin(INTERRUPT_CALLBACK callback) {
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interrupts();
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}
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void DCCTimer::startRailcomTimer(byte brakePin) {
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// TODO: for intended operation see DCCTimerAVR.cpp
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}
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void DCCTimer::ackRailcomTimer() {
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// TODO: for intended operation see DCCTimerAVR.cpp
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}
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// Timer IRQ handlers replace the dummy handlers (in cortex_handlers)
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// copied from rf24 branch
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void TCC0_Handler() {
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@ -201,6 +201,14 @@ void DCCTimer::begin(INTERRUPT_CALLBACK callback) {
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interrupts();
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}
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void DCCTimer::startRailcomTimer(byte brakePin) {
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// TODO: for intended operation see DCCTimerAVR.cpp
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}
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void DCCTimer::ackRailcomTimer() {
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// TODO: for intended operation see DCCTimerAVR.cpp
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}
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bool DCCTimer::isPWMPin(byte pin) {
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//TODO: STM32 whilst this call to digitalPinHasPWM will reveal which pins can do PWM,
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// there's no support yet for High Accuracy, so for now return false
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@ -39,6 +39,14 @@ void DCCTimer::begin(INTERRUPT_CALLBACK callback) {
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myDCCTimer.begin(interruptHandler, DCC_SIGNAL_TIME);
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}
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void DCCTimer::startRailcomTimer(byte brakePin) {
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// TODO: for intended operation see DCCTimerAVR.cpp
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}
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void DCCTimer::ackRailcomTimer() {
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// TODO: for intended operation see DCCTimerAVR.cpp
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}
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bool DCCTimer::isPWMPin(byte pin) {
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//Teensy: digitalPinHasPWM, todo
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(void) pin;
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@ -116,7 +116,21 @@ DCCWaveform::DCCWaveform( byte preambleBits, bool isMain) {
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bits_sent = 0;
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}
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volatile bool DCCWaveform::railcomActive=false; // switched on by user
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volatile bool DCCWaveform::railcomDebug=false; // switched on by user
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bool DCCWaveform::setRailcom(bool on, bool debug) {
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if (on) {
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// TODO check possible
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railcomActive=true;
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railcomDebug=debug;
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}
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else {
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railcomActive=false;
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railcomDebug=false;
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}
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return railcomActive;
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}
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#pragma GCC push_options
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#pragma GCC optimize ("-O3")
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@ -124,7 +138,6 @@ void DCCWaveform::interrupt2() {
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// calculate the next bit to be sent:
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// set state WAVE_MID_1 for a 1=bit
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// or WAVE_HIGH_0 for a 0 bit.
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if (remainingPreambles > 0 ) {
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state=WAVE_MID_1; // switch state to trigger LOW on next interrupt
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remainingPreambles--;
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@ -134,6 +147,7 @@ void DCCWaveform::interrupt2() {
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// that the reminder doesn't block a more urgent packet.
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reminderWindowOpen=transmitRepeats==0 && remainingPreambles<4 && remainingPreambles>1;
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if (remainingPreambles==1) promotePendingPacket();
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else if (remainingPreambles==10 && isMainTrack && railcomActive) DCCTimer::ackRailcomTimer();
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// Update free memory diagnostic as we don't have anything else to do this time.
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// Allow for checkAck and its called functions using 22 bytes more.
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else DCCTimer::updateMinimumFreeMemoryISR(22);
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bytes_sent = 0;
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// preamble for next packet will start...
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remainingPreambles = requiredPreambles;
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// set the railcom coundown to trigger half way
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// through the first preamble bit.
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// Note.. we are still sending the last packet bit
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// and we then have to allow for the packet end bit
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if (isMainTrack && railcomActive) DCCTimer::startRailcomTimer(9);
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}
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}
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}
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@ -208,7 +228,11 @@ void DCCWaveform::promotePendingPacket() {
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// nothing to do, just send idles or resets
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// Fortunately reset and idle packets are the same length
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memcpy( transmitPacket, isMainTrack ? idlePacket : resetPacket, sizeof(idlePacket));
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// Note: If railcomDebug is on, then we send resets to the main
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// track instead of idles. This means that all data will be zeros
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// and only the porersets will be ones, making it much
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// easier to read on a logic analyser.
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memcpy( transmitPacket, (isMainTrack && (!railcomDebug)) ? idlePacket : resetPacket, sizeof(idlePacket));
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transmitLength = sizeof(idlePacket);
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transmitRepeats = 0;
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if (getResets() < 250) sentResetsSincePacket++; // only place to increment (private!)
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@ -297,4 +321,10 @@ bool DCCWaveform::isReminderWindowOpen() {
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void IRAM_ATTR DCCWaveform::loop() {
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DCCACK::checkAck(progTrack.getResets());
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}
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bool DCCWaveform::setRailcom(bool on, bool debug) {
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// TODO... ESP32 railcom waveform
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return false;
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}
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#endif
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@ -40,7 +40,14 @@ const byte MAX_PACKET_SIZE = 5; // NMRA standard extended packets, payload s
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// The WAVE_STATE enum is deliberately numbered because a change of order would be catastrophic
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// to the transform array.
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enum WAVE_STATE : byte {WAVE_START=0,WAVE_MID_1=1,WAVE_HIGH_0=2,WAVE_MID_0=3,WAVE_LOW_0=4,WAVE_PENDING=5};
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enum WAVE_STATE : byte {
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WAVE_START=0, // wave going high at start of bit
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WAVE_MID_1=1, // middle of 1 bit
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WAVE_HIGH_0=2, // first part of 0 bit high
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WAVE_MID_0=3, // middle of 0 bit
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WAVE_LOW_0=4, // first part of 0 bit low
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WAVE_PENDING=5 // next bit not yet known
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};
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// NOTE: static functions are used for the overall controller, then
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// one instance is created for each track.
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@ -78,6 +85,8 @@ class DCCWaveform {
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void schedulePacket(const byte buffer[], byte byteCount, byte repeats);
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bool isReminderWindowOpen();
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void promotePendingPacket();
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static bool setRailcom(bool on, bool debug);
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static bool isRailcom() {return railcomActive;}
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private:
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#ifndef ARDUINO_ARCH_ESP32
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@ -103,6 +112,9 @@ class DCCWaveform {
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byte pendingPacket[MAX_PACKET_SIZE+1]; // +1 for checksum
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byte pendingLength;
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byte pendingRepeats;
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static volatile bool railcomActive; // switched on by user
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static volatile bool railcomDebug; // switched on by user
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#ifdef ARDUINO_ARCH_ESP32
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static RMTChannel *rmtMainChannel;
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static RMTChannel *rmtProgChannel;
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@ -157,12 +157,6 @@ void TrackManager::setDCCSignal( bool on) {
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HAVE_PORTF(PORTF=shadowPORTF);
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}
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void TrackManager::setCutout( bool on) {
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(void) on;
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// TODO Cutout needs fake ports as well
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// TODO APPLY_BY_MODE(TRACK_MODE_MAIN,setCutout(on));
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}
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// setPROGSignal(), called from interrupt context
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// does assume ports are shadowed if they can be
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void TrackManager::setPROGSignal( bool on) {
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@ -57,7 +57,6 @@ class TrackManager {
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);
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static void setDCCSignal( bool on);
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static void setCutout( bool on);
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static void setPROGSignal( bool on);
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static void setDCSignal(int16_t cab, byte speedbyte);
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static MotorDriver * getProgDriver();
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@ -3,7 +3,8 @@
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#include "StringFormatter.h"
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#define VERSION "5.2.31"
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#define VERSION "5.2.32"
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// 5.2.32 - Railcom Cutout (Initial trial Mega2560 only)
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// 5.2.31 - Exrail JMRI_SENSOR(vpin [,count]) creates <S> types.
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// 5.2.30 - Bugfix: WiThrottle sendIntro after initial N message as well
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// 5.2.29 - Added IO_I2CDFPlayer.h to support DFPLayer over I2C connected to NXP SC16IS750/SC16IS752 (currently only single UART for SC16IS752)
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