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I2C code corrections

Corrections to I2C code:
1) I2CManager_Mega4809.h: Correct bitwise 'and' to logical 'and' - no impact.
2) I2CManager_Wire.h: Ensure that error codes from Wire subsystem are passed back to caller in queueRequest().
This commit is contained in:
Neil McKechnie 2022-04-16 23:35:58 +01:00
parent 32fdb014ef
commit 766fdc43ac
2 changed files with 9 additions and 7 deletions

View File

@ -72,7 +72,7 @@ void I2CManagerClass::I2C_sendStart() {
bytesToReceive = currentRequest->readLen; bytesToReceive = currentRequest->readLen;
// If anything to send, initiate write. Otherwise initiate read. // If anything to send, initiate write. Otherwise initiate read.
if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) & !bytesToSend)) if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
TWI0.MADDR = (currentRequest->i2cAddress << 1) | 1; TWI0.MADDR = (currentRequest->i2cAddress << 1) | 1;
else else
TWI0.MADDR = (currentRequest->i2cAddress << 1) | 0; TWI0.MADDR = (currentRequest->i2cAddress << 1) | 0;

View File

@ -94,22 +94,24 @@ uint8_t I2CManagerClass::read(uint8_t address, uint8_t readBuffer[], uint8_t rea
/*************************************************************************** /***************************************************************************
* Function to queue a request block and initiate operations. * Function to queue a request block and initiate operations.
* *
* For the Wire version, this executes synchronously, but the status is * For the Wire version, this executes synchronously.
* returned in the I2CRB as for the asynchronous version. * The read/write/write_P functions return I2C_STATUS_OK always, and the
* completion status of the operation is in the request block, as for
* the non-blocking version.
***************************************************************************/ ***************************************************************************/
void I2CManagerClass::queueRequest(I2CRB *req) { void I2CManagerClass::queueRequest(I2CRB *req) {
switch (req->operation) { switch (req->operation) {
case OPERATION_READ: case OPERATION_READ:
req->status = read(req->i2cAddress, req->readBuffer, req->readLen, NULL, 0, req); read(req->i2cAddress, req->readBuffer, req->readLen, NULL, 0, req);
break; break;
case OPERATION_SEND: case OPERATION_SEND:
req->status = write(req->i2cAddress, req->writeBuffer, req->writeLen, req); write(req->i2cAddress, req->writeBuffer, req->writeLen, req);
break; break;
case OPERATION_SEND_P: case OPERATION_SEND_P:
req->status = write_P(req->i2cAddress, req->writeBuffer, req->writeLen, req); write_P(req->i2cAddress, req->writeBuffer, req->writeLen, req);
break; break;
case OPERATION_REQUEST: case OPERATION_REQUEST:
req->status = read(req->i2cAddress, req->readBuffer, req->readLen, req->writeBuffer, req->writeLen, req); read(req->i2cAddress, req->readBuffer, req->readLen, req->writeBuffer, req->writeLen, req);
break; break;
} }
} }