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@ -74,6 +74,7 @@ void DCCTimer::startRailcomTimer(byte brakePin) {
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- Waveform code is responsible for altering the PWM
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duty cycle to 0% any time between the first and last tick.
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(there will be 7 DCC timer1 ticks in which to do this.)
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by calling ackRailcomTimer();
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*/
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(void) brakePin; // Ignored... works on pin 9 only
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@ -99,13 +100,13 @@ void DCCTimer::startRailcomTimer(byte brakePin) {
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// Enable Timer2 output on pin 9 (OC2B)
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DDRB |= (1 << DDB1);
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// TODO Fudge TCNT2 to sync with last tcnt1 tick + 28uS
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// Fudge TCNT2 to sync with last tcnt1 tick + 28uS
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// Previous TIMER1 Tick was at rising end-of-packet bit
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// Cutout starts half way through first preamble
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// that is 2.5 * 58uS later.
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// TCNT1 ticks 8 times / microsecond
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// auto microsendsToFirstRailcomTick=(58+58+29)-(TCNT1/8);
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// Previous TIMER1 Tick was at rising end-of-packet bit
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// Cutout starts half way through first preamble
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// that is 2.5 * 58uS later.
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// TCNT1 ticks 8 times / microsecond
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// auto microsendsToFirstRailcomTick=(58+58+29)-(TCNT1/8);
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// set the railcom timer counter allowing for phase-correct
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// CHris's NOTE:
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