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https://github.com/DCC-EX/CommandStation-EX.git
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STM32 native I2C driver updates
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@ -44,6 +44,7 @@ void I2C1_IRQHandler() {
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// Assume I2C1 for now - default I2C bus on Nucleo-F411RE and likely Nucleo-64 variants
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I2C_TypeDef *s = I2C1;
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#define I2C_IRQn I2C1_EV_IRQn
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/***************************************************************************
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* Set I2C clock speed register. This should only be called outside of
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@ -109,22 +110,13 @@ void I2CManagerClass::I2C_init()
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s->CR1 |= (1<<15); // reset the I2C
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s->CR1 &= ~(1<<15); // Normal operation
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// Program the peripheral input clock in I2C_CR2 Register in order to generate correct timings
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// Program the peripheral input clock in CR2 Register in order to generate correct timings
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s->CR2 |= (16<<0); // PCLK1 FREQUENCY in MHz
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// Configure the Clock Control Register for 100KHz SCL frequency
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// Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
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// Bit 14: Duty, fast mode duty cycle
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// Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns, so CCR divisor must be 0x50 (80 * 62.5ns = 5000ns)
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s->CCR = 0x0050;
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// Configure the rise time register - max allowed in 1000ns
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s->TRISE = 0x0011; // 1000 ns / 62.5 ns = 16 + 1
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#if defined(I2C_USE_INTERRUPTS)
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// Setting NVIC
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NVIC_SetPriority(I2C1_EV_IRQn, 1); // Match default priorities
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NVIC_EnableIRQ(I2C1_EV_IRQn);
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NVIC_SetPriority(I2C_IRQn, 1); // Match default priorities
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NVIC_EnableIRQ(I2C_IRQn);
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// CR2 Interrupt Settings
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// Bit 15-13: reserved
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@ -135,14 +127,21 @@ void I2CManagerClass::I2C_init()
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// Bit 8: ITERREN - Error interrupt enable
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// Bit 7-6: reserved
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// Bit 5-0: FREQ - Peripheral clock frequency (max 50MHz)
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// Enable all interrupts
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s->CR2 |= 0x0700;
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s->CR2 |= 0x0700; // Enable Buffer, Event and Error interrupts
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#endif
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// Calculate baudrate and set default rate for now
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// Configure the Clock Control Register for 100KHz SCL frequency
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// Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
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// Bit 14: Duty, fast mode duty cycle
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// Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns, so CCR divisor must be 0x50 (80 * 62.5ns = 5000ns)
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s->CCR = 0x0050;
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// Enable the I2C master mode and wait for sync
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// Configure the rise time register - max allowed in 1000ns
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s->TRISE = 0x0011; // 1000 ns / 62.5 ns = 16 + 1
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// Enable the I2C master mode
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s->CR1 |= (1<<0); // Enable I2C
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// Setting bus idle mode and wait for sync
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}
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@ -154,6 +153,7 @@ void I2CManagerClass::I2C_sendStart() {
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// Set counters here in case this is a retry.
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bytesToSend = currentRequest->writeLen;
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bytesToReceive = currentRequest->readLen;
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uint8_t temp;
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// On a single-master I2C bus, the start bit won't be sent until the bus
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// state goes to IDLE so we can request it without waiting. On a
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@ -164,12 +164,30 @@ void I2CManagerClass::I2C_sendStart() {
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// If anything to send, initiate write. Otherwise initiate read.
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if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
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{
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// Send start and address with read flag (1) or'd in
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// s->I2CM.ADDR.bit.ADDR = (currentRequest->i2cAddress << 1) | 1;
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// Send start for read operation
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s->CR1 |= (1<<10); // Enable the ACK
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s->CR1 |= (1<<8); // Generate START
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// Send address with read flag (1) or'd in
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s->DR = (currentRequest->i2cAddress << 1) | 1; // send the address
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while (!(s->SR1 & (1<<1))); // wait for ADDR bit to set
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// Special case for 1 byte reads!
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if (bytesToReceive == 1)
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{
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s->CR1 &= ~(1<<10); // clear the ACK bit
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temp = I2C1->SR1 | I2C1->SR2; // read SR1 and SR2 to clear the ADDR bit.... EV6 condition
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s->CR1 |= (1<<9); // Stop I2C
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}
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else
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temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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else {
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// Send start and address with write flag (0) or'd in
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// s->I2CM.ADDR.bit.ADDR = (currentRequest->i2cAddress << 1ul) | 0;
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// Send start for write operation
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s->CR1 |= (1<<10); // Enable the ACK
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s->CR1 |= (1<<8); // Generate START
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// Send address with write flag (0) or'd in
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s->DR = (currentRequest->i2cAddress << 1) | 0; // send the address
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while (!(s->SR1 & (1<<1))); // wait for ADDR bit to set
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temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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}
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@ -177,7 +195,7 @@ void I2CManagerClass::I2C_sendStart() {
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* Initiate a stop bit for transmission (does not interrupt)
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***************************************************************************/
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void I2CManagerClass::I2C_sendStop() {
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// s->I2CM.CTRLB.bit.CMD = 3; // Stop condition
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s->CR1 |= (1<<9); // Stop I2C
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}
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/***************************************************************************
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@ -186,12 +204,12 @@ void I2CManagerClass::I2C_sendStop() {
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void I2CManagerClass::I2C_close() {
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I2C_sendStop();
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// Disable the I2C master mode and wait for sync
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// s->I2CM.CTRLA.bit.ENABLE = 0 ;
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// Wait for up to 500us only.
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s->CR1 &= ~(1<<0); // Disable I2C peripheral
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// Should never happen, but wait for up to 500us only.
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unsigned long startTime = micros();
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// while (s->I2CM.SYNCBUSY.bit.ENABLE != 0) {
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// if (micros() - startTime >= 500UL) break;
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// }
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while ((s->CR1 && 1) != 0) {
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if (micros() - startTime >= 500UL) break;
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}
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}
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/***************************************************************************
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@ -201,41 +219,44 @@ void I2CManagerClass::I2C_close() {
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***************************************************************************/
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void I2CManagerClass::I2C_handleInterrupt() {
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if (s->I2CM.STATUS.bit.ARBLOST) {
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if (s->SR1 && (1<<9)) {
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// Arbitration lost, restart
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I2C_sendStart(); // Reinitiate request
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} else if (s->I2CM.STATUS.bit.BUSERR) {
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} else if (s->SR1 && (1<<8)) {
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// Bus error
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state = I2C_STATUS_BUS_ERROR;
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} else if (s->I2CM.INTFLAG.bit.MB) {
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} else if (s->SR1 && (1<<7)) {
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// Master write completed
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if (s->I2CM.STATUS.bit.RXNACK) {
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if (s->SR1 && (1<<10)) {
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// Nacked, send stop.
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I2C_sendStop();
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state = I2C_STATUS_NEGATIVE_ACKNOWLEDGE;
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} else if (bytesToSend) {
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// Acked, so send next byte
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s->I2CM.DATA.bit.DATA = currentRequest->writeBuffer[txCount++];
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s->DR = currentRequest->writeBuffer[txCount++];
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bytesToSend--;
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} else if (bytesToReceive) {
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// Last sent byte acked and no more to send. Send repeated start, address and read bit.
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s->I2CM.ADDR.bit.ADDR = (currentRequest->i2cAddress << 1) | 1;
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// s->I2CM.ADDR.bit.ADDR = (currentRequest->i2cAddress << 1) | 1;
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} else {
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// Check both TxE/BTF == 1 before generating stop
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while (!(s->SR1 && (1<<7))); // Check TxE
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while (!(s->SR1 && (1<<2))); // Check BTF
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// No more data to send/receive. Initiate a STOP condition.
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I2C_sendStop();
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state = I2C_STATUS_OK; // Done
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}
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} else if (s->I2CM.INTFLAG.bit.SB) {
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} else if (s->SR1 && (1<<6)) {
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// Master read completed without errors
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if (bytesToReceive == 1) {
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s->I2CM.CTRLB.bit.ACKACT = 1; // NAK final byte
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// s->I2CM.CTRLB.bit.ACKACT = 1; // NAK final byte
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I2C_sendStop(); // send stop
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currentRequest->readBuffer[rxCount++] = s->I2CM.DATA.bit.DATA; // Store received byte
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currentRequest->readBuffer[rxCount++] = s->DR; // Store received byte
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bytesToReceive = 0;
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state = I2C_STATUS_OK; // done
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} else if (bytesToReceive) {
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s->I2CM.CTRLB.bit.ACKACT = 0; // ACK all but final byte
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currentRequest->readBuffer[rxCount++] = s->I2CM.DATA.bit.DATA; // Store received byte
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// s->I2CM.CTRLB.bit.ACKACT = 0; // ACK all but final byte
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currentRequest->readBuffer[rxCount++] = s->DR; // Store received byte
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bytesToReceive--;
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}
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}
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