mirror of
https://github.com/DCC-EX/CommandStation-EX.git
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Merge branch 'devel-nmck' of https://github.com/DCC-EX/CommandStation-EX into devel-nmck
This commit is contained in:
Neil McKechnie
commit
f5b5809ba5
@ -55,7 +55,7 @@ void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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// Calculate a rise time appropriate to the requested bus speed
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int t_rise;
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if (i2cClockSpeed < 200000L) {
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i2cClockSpeed = 100000L;
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i2cClockSpeed = 100000L; // NB: this overrides a "force clock" of lower than 100KHz!
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t_rise = 1000;
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} else if (i2cClockSpeed < 800000L) {
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i2cClockSpeed = 400000L;
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@ -45,6 +45,39 @@ void I2C1_IRQHandler() {
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// Assume I2C1 for now - default I2C bus on Nucleo-F411RE and likely Nucleo-64 variants
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I2C_TypeDef *s = I2C1;
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#define I2C_IRQn I2C1_EV_IRQn
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#define I2C_BUSFREQ 16
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// I2C SR1 Status Register #1 bit definitions for convenience
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// #define I2C_SR1_SMBALERT (1<<15) // SMBus alert
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// #define I2C_SR1_TIMEOUT (1<<14) // Timeout of Tlow error
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// #define I2C_SR1_PECERR (1<<12) // PEC error in reception
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// #define I2C_SR1_OVR (1<<11) // Overrun/Underrun error
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// #define I2C_SR1_AF (1<<10) // Acknowledge failure
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// #define I2C_SR1_ARLO (1<<9) // Arbitration lost (master mode)
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// #define I2C_SR1_BERR (1<<8) // Bus error (misplaced start or stop condition)
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// #define I2C_SR1_TxE (1<<7) // Data register empty on transmit
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// #define I2C_SR1_RxNE (1<<6) // Data register not empty on receive
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// #define I2C_SR1_STOPF (1<<4) // Stop detection (slave mode)
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// #define I2C_SR1_ADD10 (1<<3) // 10 bit header sent
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// #define I2C_SR1_BTF (1<<2) // Byte transfer finished - data transfer done
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// #define I2C_SR1_ADDR (1<<1) // Address sent (master) or matched (slave)
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// #define I2C_SR1_SB (1<<0) // Start bit (master mode) 1=start condition generated
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// I2C CR1 Control Register #1 bit definitions for convenience
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// #define I2C_CR1_SWRST (1<<15) // Software reset - places peripheral under reset
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// #define I2C_CR1_ALERT (1<<13) // SMBus alert assertion
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// #define I2C_CR1_PEC (1<<12) // Packet Error Checking transfer in progress
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// #define I2C_CR1_POS (1<<11) // Acknowledge/PEC Postion (for data reception in PEC mode)
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// #define I2C_CR1_ACK (1<<10) // Acknowledge enable - ACK returned after byte is received (address or data)
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// #define I2C_CR1_STOP (1<<9) // STOP generated
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// #define I2C_CR1_START (1<<8) // START generated
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// #define I2C_CR1_NOSTRETCH (1<<7) // Clock stretching disable (slave mode)
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// #define I2C_CR1_ENGC (1<<6) // General call (broadcast) enable (address 00h is ACKed)
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// #define I2C_CR1_ENPEC (1<<5) // PEC Enable
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// #define I2C_CR1_ENARP (1<<4) // ARP enable (SMBus)
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// #define I2C_CR1_SMBTYPE (1<<3) // SMBus type, 1=host, 0=device
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// #define I2C_CR1_SMBUS (1<<1) // SMBus mode, 1=SMBus, 0=I2C
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// #define I2C_CR1_PE (1<<0) // I2C Peripheral enable
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/***************************************************************************
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* Set I2C clock speed register. This should only be called outside of
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@ -54,36 +87,47 @@ I2C_TypeDef *s = I2C1;
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void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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// Calculate a rise time appropriate to the requested bus speed
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int t_rise;
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// Use 10x the rise time spec to enable integer divide of 62.5ns clock period
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uint16_t t_rise;
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uint32_t ccr_freq;
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if (i2cClockSpeed < 200000L) {
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i2cClockSpeed = 100000L;
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t_rise = 1000;
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} else if (i2cClockSpeed < 800000L) {
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// i2cClockSpeed = 100000L;
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t_rise = 0x11; // (1000ns /62.5ns) + 1;
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}
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else if (i2cClockSpeed < 800000L)
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{
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i2cClockSpeed = 400000L;
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t_rise = 300;
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} else if (i2cClockSpeed < 1200000L) {
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i2cClockSpeed = 1000000L;
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t_rise = 120;
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} else {
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t_rise = 0x06; // (300ns / 62.5ns) + 1;
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// } else if (i2cClockSpeed < 1200000L) {
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// i2cClockSpeed = 1000000L;
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// t_rise = 120;
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}
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else
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{
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i2cClockSpeed = 100000L;
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t_rise = 1000;
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t_rise = 0x11; // (1000ns /62.5ns) + 1;
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}
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// Disable the I2C master mode and wait for sync
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// s->I2CM.CTRLA.bit.ENABLE = 0 ;
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// while (s->I2CM.SYNCBUSY.bit.ENABLE != 0);
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// Enable the I2C master mode
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s->CR1 &= ~(I2C_CR1_PE); // Enable I2C
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// Software reset the I2C peripheral
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// s->CR1 |= I2C_CR1_SWRST; // reset the I2C
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// Release reset
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// s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
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// Calculate baudrate - using a rise time appropriate for the speed
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// s->I2CM.BAUD.bit.BAUD = SystemCoreClock / (2 * i2cClockSpeed) - 5 - (((SystemCoreClock / 1000000) * t_rise) / (2 * 1000));
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ccr_freq = I2C_BUSFREQ * 1000000 / i2cClockSpeed / 2;
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// Enable the I2C master mode and wait for sync
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// s->I2CM.CTRLA.bit.ENABLE = 1 ;
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// while (s->I2CM.SYNCBUSY.bit.ENABLE != 0);
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// Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
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// Bit 14: Duty, fast mode duty cycle
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// Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns, so CCR divisor must be 0x50 (80 * 62.5ns = 5000ns)
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s->CCR = (uint16_t)ccr_freq;
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// Setting bus idle mode and wait for sync
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// s->I2CM.STATUS.bit.BUSSTATE = 1 ;
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// while (s->I2CM.SYNCBUSY.bit.SYSOP != 0);
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// Configure the rise time register
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s->TRISE = t_rise; // 1000 ns / 62.5 ns = 16 + 1
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// Enable the I2C master mode
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s->CR1 |= I2C_CR1_PE; // Enable I2C
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}
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/***************************************************************************
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@ -107,11 +151,11 @@ void I2CManagerClass::I2C_init()
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GPIOB->AFR[1] |= (4<<0) | (4<<4); // PB8 on low nibble, PB9 on next nibble up
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// Software reset the I2C peripheral
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s->CR1 |= (1<<15); // reset the I2C
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s->CR1 &= ~(1<<15); // Normal operation
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s->CR1 |= I2C_CR1_SWRST; // reset the I2C
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s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
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// Program the peripheral input clock in CR2 Register in order to generate correct timings
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s->CR2 |= (16<<0); // PCLK1 FREQUENCY in MHz
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s->CR2 |= I2C_BUSFREQ; // PCLK1 FREQUENCY in MHz
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#if defined(I2C_USE_INTERRUPTS)
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// Setting NVIC
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@ -127,7 +171,8 @@ void I2CManagerClass::I2C_init()
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// Bit 8: ITERREN - Error interrupt enable
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// Bit 7-6: reserved
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// Bit 5-0: FREQ - Peripheral clock frequency (max 50MHz)
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s->CR2 |= 0x0700; // Enable Buffer, Event and Error interrupts
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// s->CR2 |= 0x0700; // Enable Buffer, Event and Error interrupts
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s->CR2 |= 0x0300; // Enable Event and Error interrupts
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#endif
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// Calculate baudrate and set default rate for now
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@ -141,7 +186,7 @@ void I2CManagerClass::I2C_init()
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s->TRISE = 0x0011; // 1000 ns / 62.5 ns = 16 + 1
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// Enable the I2C master mode
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s->CR1 |= (1<<0); // Enable I2C
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s->CR1 |= I2C_CR1_PE; // Enable I2C
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// Setting bus idle mode and wait for sync
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}
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@ -164,28 +209,28 @@ void I2CManagerClass::I2C_sendStart() {
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if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
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{
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// Send start for read operation
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s->CR1 |= (1<<10); // Enable the ACK
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s->CR1 |= (1<<8); // Generate START
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s->CR1 |= I2C_CR1_ACK; // Enable the ACK
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s->CR1 |= I2C_CR1_START; // Generate START
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// Send address with read flag (1) or'd in
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s->DR = (deviceAddress << 1) | 1; // send the address
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while (!(s->SR1 & (1<<1))); // wait for ADDR bit to set
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while (!(s->SR1 && I2C_SR1_ADDR)); // wait for ADDR bit to set
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// Special case for 1 byte reads!
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if (bytesToReceive == 1)
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{
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s->CR1 &= ~(1<<10); // clear the ACK bit
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s->CR1 &= ~I2C_CR1_ACK; // clear the ACK bit
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temp = I2C1->SR1 | I2C1->SR2; // read SR1 and SR2 to clear the ADDR bit.... EV6 condition
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s->CR1 |= (1<<9); // Stop I2C
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s->CR1 |= I2C_CR1_STOP; // Stop I2C
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}
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else
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temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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else {
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// Send start for write operation
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s->CR1 |= (1<<10); // Enable the ACK
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s->CR1 |= (1<<8); // Generate START
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s->CR1 |= I2C_CR1_ACK; // Enable the ACK
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s->CR1 |= I2C_CR1_START; // Generate START
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// Send address with write flag (0) or'd in
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s->DR = (deviceAddress << 1) | 0; // send the address
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while (!(s->SR1 & (1<<1))); // wait for ADDR bit to set
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while (!(s->SR1 && (1<<I2C_SR1_ADDR))); // wait for ADDR bit to set
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temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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}
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@ -194,7 +239,7 @@ void I2CManagerClass::I2C_sendStart() {
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* Initiate a stop bit for transmission (does not interrupt)
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***************************************************************************/
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void I2CManagerClass::I2C_sendStop() {
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s->CR1 |= (1<<9); // Stop I2C
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s->CR1 |= I2C_CR1_STOP; // Stop I2C
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}
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/***************************************************************************
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@ -203,10 +248,10 @@ void I2CManagerClass::I2C_sendStop() {
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void I2CManagerClass::I2C_close() {
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I2C_sendStop();
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// Disable the I2C master mode and wait for sync
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s->CR1 &= ~(1<<0); // Disable I2C peripheral
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s->CR1 &= ~I2C_CR1_PE; // Disable I2C peripheral
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// Should never happen, but wait for up to 500us only.
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unsigned long startTime = micros();
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while ((s->CR1 && 1) != 0) {
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while ((s->CR1 && I2C_CR1_PE) != 0) {
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if (micros() - startTime >= 500UL) break;
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}
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}
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@ -218,16 +263,14 @@ void I2CManagerClass::I2C_close() {
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***************************************************************************/
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void I2CManagerClass::I2C_handleInterrupt() {
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if (!s) return;
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if (s->SR1 && (1<<9)) {
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if (s->SR1 && I2C_SR1_ARLO) {
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// Arbitration lost, restart
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I2C_sendStart(); // Reinitiate request
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} else if (s->SR1 && (1<<8)) {
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} else if (s->SR1 && I2C_SR1_BERR) {
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// Bus error
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completionStatus = I2C_STATUS_BUS_ERROR;
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state = I2C_STATE_COMPLETED;
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} else if (s->SR1 && (1<<7)) {
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} else if (s->SR1 && (1<<I2C_SR1_TXE)) {
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// Master write completed
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if (s->SR1 && (1<<10)) {
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// Nacked, send stop.
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@ -243,13 +286,13 @@ void I2CManagerClass::I2C_handleInterrupt() {
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// s->I2CM.ADDR.bit.ADDR = (deviceAddress << 1) | 1;
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} else {
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// Check both TxE/BTF == 1 before generating stop
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while (!(s->SR1 && (1<<7))); // Check TxE
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while (!(s->SR1 && (1<<2))); // Check BTF
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while (!(s->SR1 && I2C_SR1_TXE)); // Check TxE
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while (!(s->SR1 && I2C_SR1_BTF)); // Check BTF
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// No more data to send/receive. Initiate a STOP condition and finish
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I2C_sendStop();
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state = I2C_STATE_COMPLETED;
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}
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} else if (s->SR1 && (1<<6)) {
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} else if (s->SR1 && I2C_SR1_RXNE) {
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// Master read completed without errors
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if (bytesToReceive == 1) {
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// s->I2CM.CTRLB.bit.ACKACT = 1; // NAK final byte
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