I2CManager.cpp

@@ -92,7 +92,7 @@ void I2CManagerClass::begin(void) {
     // Probe and list devices.  Use standard mode 
     //  (clock speed 100kHz) for best device compatibility.
     _setClock(100000);
-    uint32_t originalTimeout = _timeout;
+    unsigned long originalTimeout = _timeout;
     setTimeout(1000);       // use 1ms timeout for probes
 
   #if defined(I2C_EXTENDED_ADDRESS)

I2CManager.h

@@ -485,7 +485,7 @@ private:
   // When retries are enabled, the timeout applies to each
   // try, and failure from timeout does not get retried.
   // A value of 0 means disable timeout monitoring.
-  uint32_t _timeout = 100000UL;
+  unsigned long _timeout = 100000UL;
     
   // Finish off request block by waiting for completion and posting status.
   uint8_t finishRB(I2CRB *rb, uint8_t status);
@@ -532,15 +532,14 @@ private:
     uint8_t bytesToSend = 0;
     uint8_t bytesToReceive = 0;
     uint8_t operation = 0;
-    uint32_t startTime = 0;
+    unsigned long startTime = 0;
     uint8_t muxPhase = 0;
     uint8_t muxAddress = 0;
     uint8_t muxData[1];
     uint8_t deviceAddress;
     const uint8_t *sendBuffer;
     uint8_t *receiveBuffer;
-    uint8_t transactionState = 0;
+
-  
     volatile uint32_t pendingClockSpeed = 0;
 
     void startTransaction();

I2CManager_NonBlocking.h

@@ -172,10 +172,6 @@ void I2CManagerClass::startTransaction() {
  *  Function to queue a request block and initiate operations.
  ***************************************************************************/
 void I2CManagerClass::queueRequest(I2CRB *req) {
-
-  if (((req->operation & OPERATION_MASK) == OPERATION_READ) && req->readLen == 0)
-    return;  // Ignore null read
-
   req->status = I2C_STATUS_PENDING;
   req->nextRequest = NULL;
   ATOMIC_BLOCK() {
@@ -188,7 +184,6 @@ void I2CManagerClass::queueRequest(I2CRB *req) {
 
 }
 
-
 /***************************************************************************
  *  Initiate a write to an I2C device (non-blocking operation)
  ***************************************************************************/
@@ -245,8 +240,8 @@ void I2CManagerClass::checkForTimeout() {
     I2CRB *t = queueHead;
     if (state==I2C_STATE_ACTIVE && t!=0 && t==currentRequest && _timeout > 0) {
       // Check for timeout
-      int32_t elapsed = micros() - startTime;
+      unsigned long elapsed = micros() - startTime;
-      if (elapsed > (int32_t)_timeout) { 
+      if (elapsed > _timeout) { 
 #ifdef DIAG_IO
         //DIAG(F("I2CManager Timeout on %s"), t->i2cAddress.toString());
 #endif
@@ -305,12 +300,12 @@ void I2CManagerClass::handleInterrupt() {
 
   // Check if current request has completed.  If there's a current request
   // and state isn't active then state contains the completion status of the request.
-  if (state == I2C_STATE_COMPLETED && currentRequest != NULL && currentRequest == queueHead) {
+  if (state == I2C_STATE_COMPLETED && currentRequest != NULL) {
     // Operation has completed.
     if (completionStatus == I2C_STATUS_OK || ++retryCounter > MAX_I2C_RETRIES
       || currentRequest->operation & OPERATION_NORETRY) 
     {
-      // Status is OK, or has failed and retry count exceeded, or failed and retries disabled.
+      // Status is OK, or has failed and retry count exceeded, or retries disabled.
 #if defined(I2C_EXTENDED_ADDRESS)
       if (muxPhase == MuxPhase_PROLOG ) {
         overallStatus = completionStatus;

I2CManager_STM32.h

@@ -26,42 +26,27 @@
 #include "I2CManager.h"
 #include "I2CManager_NonBlocking.h"   // to satisfy intellisense
 
+//#include <avr/io.h>
+//#include <avr/interrupt.h>
 #include <wiring_private.h>
-#include "stm32f4xx_hal_rcc.h"
 
-/*****************************************************************************
+/***************************************************************************
- *  STM32F4xx I2C native driver support
+ *  Interrupt handler.
- * 
+ *  IRQ handler for SERCOM3 which is the default I2C definition for Arduino Zero
- *  Nucleo-64 and Nucleo-144 boards all use I2C1 as the default I2C peripheral
+ *  compatible variants such as the Sparkfun SAMD21 Dev Breakout etc.
- *  Later we may wish to support other STM32 boards, allow use of an alternate
+ *  Later we may wish to allow use of an alternate I2C bus, or more than one I2C
- *  I2C bus, or more than one I2C bus on the STM32 architecture 
+ *  bus on the SAMD architecture 
- *****************************************************************************/
+ ***************************************************************************/
 #if defined(I2C_USE_INTERRUPTS) && defined(ARDUINO_ARCH_STM32)
-#if defined(ARDUINO_NUCLEO_F411RE) || defined(ARDUINO_NUCLEO_F446RE) || defined(ARDUINO_NUCLEO_F412ZG) || defined(ARDUINO_NUCLEO_F429ZI) || defined(ARDUINO_NUCLEO_F446ZE)
+void I2C1_IRQHandler() {
-// Assume I2C1 for now - default I2C bus on Nucleo-F411RE and likely all Nucleo-64
+  I2CManager.handleInterrupt();
-// and Nucleo-144variants
+}
+#endif
+
+// Assume I2C1 for now - default I2C bus on Nucleo-F411RE and likely Nucleo-64 variants
 I2C_TypeDef *s = I2C1;
-
+#define I2C_IRQn  I2C1_EV_IRQn
-// In init we will ask the STM32 HAL layer for the configured APB1 clock frequency in Hz
+#define I2C_BUSFREQ 16
-uint32_t APB1clk1; // Peripheral Input Clock speed in Hz.
-uint32_t i2c_MHz;  // Peripheral Input Clock speed in MHz.
-
-// IRQ handler for I2C1, replacing the weak definition in the STM32 HAL 
-extern "C" void I2C1_EV_IRQHandler(void) {
-  I2CManager.handleInterrupt();
-}
-extern "C" void I2C1_ER_IRQHandler(void) {
-  I2CManager.handleInterrupt();
-}
-#else
-#warning STM32 board selected is not yet supported - so I2C1 peripheral is not defined
-#endif
-#endif
-
-// Peripheral Input Clock speed in MHz.
-// For STM32F446RE, the speed is 45MHz.  Ideally, this should be determined
-// at run-time from the APB1 clock, as it can vary from STM32 family to family.
-// #define I2C_PERIPH_CLK 45
 
 // I2C SR1 Status Register #1 bit definitions for convenience
 // #define I2C_SR1_SMBALERT  (1<<15)   // SMBus alert
@@ -95,55 +80,52 @@ extern "C" void I2C1_ER_IRQHandler(void) {
 // #define I2C_CR1_SMBUS     (1<<1)    // SMBus mode, 1=SMBus, 0=I2C
 // #define I2C_CR1_PE        (1<<0)    // I2C Peripheral enable
 
-// States of the STM32 I2C driver state machine
-enum {TS_IDLE,TS_START,TS_W_ADDR,TS_W_DATA,TS_W_STOP,TS_R_ADDR,TS_R_DATA,TS_R_STOP};
-
-
 /***************************************************************************
  *  Set I2C clock speed register.  This should only be called outside of
  *  a transmission.  The I2CManagerClass::_setClock() function ensures 
  *  that it is only called at the beginning of an I2C transaction.
  ***************************************************************************/
 void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
+
   // Calculate a rise time appropriate to the requested bus speed
-  // Use 10x the rise time spec to enable integer divide of 50ns clock period
+  // Use 10x the rise time spec to enable integer divide of 62.5ns clock period
   uint16_t t_rise;
   uint32_t ccr_freq;
-
+  if (i2cClockSpeed < 200000L) {
-  while (s->CR1 & I2C_CR1_STOP);  // Prevents lockup by guarding further
+    // i2cClockSpeed = 100000L;
-                                  // writes to CR1 while STOP is being executed!
+    t_rise = 0x11;  // (1000ns /62.5ns) + 1;
-
+  }
-  // Disable the I2C device, as TRISE can only be programmed whilst disabled
+  else if (i2cClockSpeed < 800000L)
-  s->CR1 &= ~(I2C_CR1_PE);  // Disable I2C
-
-  if (i2cClockSpeed > 100000L)
   {
-    if (i2cClockSpeed > 400000L)
+    i2cClockSpeed = 400000L;
-      i2cClockSpeed = 400000L;
+    t_rise = 0x06;  // (300ns / 62.5ns) + 1;
-
+    // } else if (i2cClockSpeed < 1200000L) {
-    t_rise = 300;  // nanoseconds
+    //   i2cClockSpeed = 1000000L;
+    //   t_rise = 120;
   }
   else
   {
     i2cClockSpeed = 100000L;
-    t_rise = 1000;  // nanoseconds
+    t_rise = 0x11;  // (1000ns /62.5ns) + 1;
   }
-  // Configure the rise time register
+
-  s->TRISE = (t_rise / (1000 / i2c_MHz)) + 1;
+  // Enable the I2C master mode
+  s->CR1 &= ~(I2C_CR1_PE);  // Enable I2C
+  // Software reset the I2C peripheral
+  // s->CR1 |= I2C_CR1_SWRST;  // reset the I2C
+  // Release reset
+  // s->CR1 &= ~(I2C_CR1_SWRST);  // Normal operation
+
+  // Calculate baudrate - using a rise time appropriate for the speed
+  ccr_freq = I2C_BUSFREQ * 1000000 / i2cClockSpeed / 2;
 
   // Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
-  // Bit 14: Duty, fast mode duty cycle (use 2:1)
+  // Bit 14: Duty, fast mode duty cycle
-  // Bit 11-0: FREQR
+  // Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns, so CCR divisor must be 0x50 (80 * 62.5ns = 5000ns)
-  if (i2cClockSpeed > 100000L) {
+  s->CCR = (uint16_t)ccr_freq;
-    // In fast mode, I2C period is 3 * CCR * TPCLK1.
+
-    //APB1clk1 / 3 / i2cClockSpeed = 38, but that results in 306KHz not 400! 
+  // Configure the rise time register
-    ccr_freq = 30;     // So 30 gives 396KHz or so!
+  s->TRISE = t_rise;  // 1000 ns / 62.5 ns = 16 + 1
-    s->CCR = (uint16_t)(ccr_freq | 0x8000); // We need Fast Mode set
-  } else {
-    // In standard mode, I2C period is 2 * CCR * TPCLK1
-    ccr_freq = (APB1clk1 / 2 / i2cClockSpeed); // Should be 225 for 45Mhz APB1 clock
-    s->CCR |= (uint16_t)ccr_freq;
-  }
 
   // Enable the I2C master mode
   s->CR1 |= I2C_CR1_PE;  // Enable I2C
@@ -154,51 +136,32 @@ void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
  ***************************************************************************/
 void I2CManagerClass::I2C_init()
 {
-  // Query the clockspeed from the STM32 HAL layer
+  //Setting up the clocks
-  APB1clk1 = HAL_RCC_GetPCLK1Freq();
+  RCC->APB1ENR |= (1<<21);  // Enable I2C CLOCK
-  i2c_MHz = APB1clk1 / 1000000UL;
-  // Enable clocks
-  RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;//(1 << 21); // Enable I2C CLOCK
-  // Reset the I2C1 peripheral to initial state
-  RCC->APB1RSTR |=  RCC_APB1RSTR_I2C1RST;
-	RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C1RST;
-  // Standard I2C pins are SCL on PB8 and SDA on PB9
   RCC->AHB1ENR |= (1<<1);   // Enable GPIOB CLOCK for PB8/PB9
+  // Standard I2C pins are SCL on PB8 and SDA on PB9
   // Bits (17:16)= 1:0 --> Alternate Function for Pin PB8;
   // Bits (19:18)= 1:0 --> Alternate Function for Pin PB9
-  GPIOB->MODER &= ~((3<<(8*2)) | (3<<(9*2)));    // Clear all MODER bits for PB8 and PB9
   GPIOB->MODER |= (2<<(8*2)) | (2<<(9*2));    // PB8 and PB9 set to ALT function
   GPIOB->OTYPER |= (1<<8) | (1<<9);           // PB8 and PB9 set to open drain output capability
   GPIOB->OSPEEDR |= (3<<(8*2)) | (3<<(9*2));  // PB8 and PB9 set to High Speed mode
-  GPIOB->PUPDR &= ~((3<<(8*2)) | (3<<(9*2))); // Clear all PUPDR bits for PB8 and PB9
   GPIOB->PUPDR |= (1<<(8*2)) | (1<<(9*2));    // PB8 and PB9 set to pull-up capability
   // Alt Function High register routing pins PB8 and PB9 for I2C1:
   // Bits (3:2:1:0) = 0:1:0:0 --> AF4 for pin PB8
   // Bits (7:6:5:4) = 0:1:0:0 --> AF4 for pin PB9
-  GPIOB->AFR[1] &= ~((15<<0) | (15<<4));      // Clear all AFR bits for PB8 on low nibble, PB9 on next nibble up
   GPIOB->AFR[1] |= (4<<0) | (4<<4);           // PB8 on low nibble, PB9 on next nibble up
 
   // Software reset the I2C peripheral
   s->CR1 |= I2C_CR1_SWRST;  // reset the I2C
-  asm("nop");    // wait a bit... suggestion from online!
+  s->CR1 &= ~(I2C_CR1_SWRST);  // Normal operation
-  s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
 
-  // Clear all bits in I2C CR2 register except reserved bits
+  // Program the peripheral input clock in CR2 Register in order to generate correct timings
-  s->CR2 &= 0xE000;
+  s->CR2 |= I2C_BUSFREQ;  // PCLK1 FREQUENCY in MHz
-
-  // Set I2C peripheral clock frequency
-  // s->CR2 |= I2C_PERIPH_CLK;
-  s->CR2 |= i2c_MHz;
-
-  // set own address to 00 - not used in master mode
-  I2C1->OAR1 = (1 << 14); // bit 14 should be kept at 1 according to the datasheet
 
 #if defined(I2C_USE_INTERRUPTS)
   // Setting NVIC
-  NVIC_SetPriority(I2C1_EV_IRQn, 1);  // Match default priorities
+  NVIC_SetPriority(I2C_IRQn, 1);  // Match default priorities
-  NVIC_EnableIRQ(I2C1_EV_IRQn);
+  NVIC_EnableIRQ(I2C_IRQn);
-  NVIC_SetPriority(I2C1_ER_IRQn, 1);  // Match default priorities
-  NVIC_EnableIRQ(I2C1_ER_IRQn);
 
   // CR2 Interrupt Settings
   // Bit 15-13: reserved
@@ -209,25 +172,23 @@ void I2CManagerClass::I2C_init()
   // Bit 8: ITERREN - Error interrupt enable
   // Bit 7-6: reserved
   // Bit 5-0: FREQ - Peripheral clock frequency (max 50MHz)
-  s->CR2 |= (I2C_CR2_ITBUFEN | I2C_CR2_ITEVTEN | I2C_CR2_ITERREN);   // Enable Buffer, Event and Error interrupts
+  // s->CR2 |= 0x0700;   // Enable Buffer, Event and Error interrupts
+  s->CR2 |= 0x0300;   // Enable Event and Error interrupts
 #endif
 
   // Calculate baudrate and set default rate for now
   // Configure the Clock Control Register for 100KHz SCL frequency
   // Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
   // Bit 14: Duty, fast mode duty cycle
-  // Bit 11-0: so CCR divisor would be clk / 2 / 100000 (where clk is in Hz)
+  // Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns, so CCR divisor must be 0x50 (80 * 62.5ns = 5000ns)
-  // s->CCR = I2C_PERIPH_CLK * 5;
+  s->CCR = 0x0050;
-  s->CCR &= ~(0x3000); // Clear all bits except 12 and 13 which must remain per reset value
-  s->CCR |= (APB1clk1 / 2 / 100000UL); // i2c_MHz * 5;
-  // s->CCR = i2c_MHz * 5;
 
-  // Configure the rise time register - max allowed is 1000ns, so value = 1000ns * I2C_PERIPH_CLK MHz / 1000 + 1.
+  // Configure the rise time register - max allowed in 1000ns
-  // s->TRISE = I2C_PERIPH_CLK + 1;    // 1000 ns / 50 ns = 20 + 1 = 21
+  s->TRISE = 0x0011; // 1000 ns / 62.5 ns = 16 + 1
-  s->TRISE = i2c_MHz + 1;
 
   // Enable the I2C master mode
   s->CR1 |= I2C_CR1_PE;  // Enable I2C
+  // Setting bus idle mode and wait for sync
 }
 
 /***************************************************************************
@@ -237,30 +198,49 @@ void I2CManagerClass::I2C_sendStart() {
 
   // Set counters here in case this is a retry.
   rxCount = txCount = 0;
+  uint8_t temp;
 
-  // On a single-master I2C bus, the start bit won't be sent until the bus
+  // On a single-master I2C bus, the start bit won't be sent until the bus 
-  // state goes to IDLE so we can request it without waiting.  On a
+  // state goes to IDLE so we can request it without waiting.  On a 
-  // multi-master bus, the bus may be BUSY under control of another master,
+  // multi-master bus, the bus may be BUSY under control of another master, 
   // in which case we can avoid some arbitration failures by waiting until
   // the bus state is IDLE.  We don't do that here.
-  //while (s->SR2 & I2C_SR2_BUSY) {}
 
-  // Check there's no STOP still in progress.  If we OR the START bit into CR1
+  // If anything to send, initiate write.  Otherwise initiate read.
-  // and the STOP bit is already set, we could output multiple STOP conditions.
+  if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
-  while (s->CR1 & I2C_CR1_STOP) {}  // Wait for STOP bit to reset
+  {
-
+    // Send start for read operation
-  s->CR2 |= (I2C_CR2_ITEVTEN | I2C_CR2_ITERREN);  // Enable interrupts
+    s->CR1 |= I2C_CR1_ACK;  // Enable the ACK
-  s->CR2 &= ~I2C_CR2_ITBUFEN;     // Don't enable buffer interupts yet.
+    s->CR1 |= I2C_CR1_START;  // Generate START
-  s->CR1 &= ~I2C_CR1_POS;   // Clear the POS bit
+    // Send address with read flag (1) or'd in
-  s->CR1 |= (I2C_CR1_ACK | I2C_CR1_START);   // Enable the ACK and generate START
+    s->DR = (deviceAddress << 1) | 1;  //  send the address
-  transactionState = TS_START;
+    while (!(s->SR1 && I2C_SR1_ADDR));  // wait for ADDR bit to set
+    // Special case for 1 byte reads!
+    if (bytesToReceive == 1)
+    {
+      s->CR1 &= ~I2C_CR1_ACK;            // clear the ACK bit 
+		  temp = I2C1->SR1 | I2C1->SR2;  // read SR1 and SR2 to clear the ADDR bit.... EV6 condition
+		  s->CR1 |= I2C_CR1_STOP;              // Stop I2C
+    }
+    else
+      temp = s->SR1 | s->SR2;        // read SR1 and SR2 to clear the ADDR bit
+  }
+  else {
+    // Send start for write operation
+    s->CR1 |= I2C_CR1_ACK;  // Enable the ACK
+    s->CR1 |= I2C_CR1_START;  // Generate START
+    // Send address with write flag (0) or'd in
+    s->DR = (deviceAddress << 1) | 0;  //  send the address
+    while (!(s->SR1 && I2C_SR1_ADDR));  // wait for ADDR bit to set
+    temp = s->SR1 | s->SR2;  // read SR1 and SR2 to clear the ADDR bit
+  }
 }
 
 /***************************************************************************
  *  Initiate a stop bit for transmission (does not interrupt)
  ***************************************************************************/
 void I2CManagerClass::I2C_sendStop() {
-  s->CR1 |= I2C_CR1_STOP; // Stop I2C
+  s->CR1 |= I2C_CR1_STOP;              // Stop I2C
 }
 
 /***************************************************************************
@@ -272,11 +252,9 @@ void I2CManagerClass::I2C_close() {
   s->CR1 &= ~I2C_CR1_PE;  // Disable I2C peripheral
   // Should never happen, but wait for up to 500us only.
   unsigned long startTime = micros();
-  while ((s->CR1 & I2C_CR1_PE) != 0) {
+  while ((s->CR1 && I2C_CR1_PE) != 0) {
-    if ((int32_t)(micros() - startTime) >= 500) break;
+    if (micros() - startTime >= 500UL) break;
   }
-  NVIC_DisableIRQ(I2C1_EV_IRQn);
-  NVIC_DisableIRQ(I2C1_ER_IRQn);
 }
 
 /***************************************************************************
@@ -285,217 +263,50 @@ void I2CManagerClass::I2C_close() {
  *  (and therefore, indirectly, from I2CRB::wait() and I2CRB::isBusy()).
  ***************************************************************************/
 void I2CManagerClass::I2C_handleInterrupt() {
-  volatile uint16_t temp_sr1, temp_sr2;
 
-  temp_sr1 = s->SR1;
+  if (s->SR1 && I2C_SR1_ARLO) {
-
+    // Arbitration lost, restart
-  // Check for errors first
+    I2C_sendStart();   // Reinitiate request
-  if (temp_sr1 & (I2C_SR1_AF | I2C_SR1_ARLO | I2C_SR1_BERR)) {
+  } else if (s->SR1 && I2C_SR1_BERR) {
-    // Check which error flag is set
+    // Bus error
-    if (temp_sr1 & I2C_SR1_AF)
+    completionStatus = I2C_STATUS_BUS_ERROR;
-    {
+    state = I2C_STATE_COMPLETED;
-      s->SR1 &= ~(I2C_SR1_AF); // Clear AF
+  } else if (s->SR1 && I2C_SR1_TXE) {
-      I2C_sendStop(); // Clear the bus
+    // Master write completed
-      transactionState = TS_IDLE;
+    if (s->SR1 && (1<<10)) {
+      // Nacked, send stop.
+      I2C_sendStop();
       completionStatus = I2C_STATUS_NEGATIVE_ACKNOWLEDGE;
       state = I2C_STATE_COMPLETED;
-    }
+    } else if (bytesToSend) {
-    else if (temp_sr1 & I2C_SR1_ARLO)
+      // Acked, so send next byte
-    {
+      s->DR = sendBuffer[txCount++];
-      // Arbitration lost, restart
+      bytesToSend--;
-      s->SR1 &= ~(I2C_SR1_ARLO); // Clear ARLO
+    } else if (bytesToReceive) {
-      I2C_sendStart(); // Reinitiate request
+      // Last sent byte acked and no more to send.  Send repeated start, address and read bit.
-      transactionState = TS_START;
+      // s->I2CM.ADDR.bit.ADDR = (deviceAddress << 1) | 1;
-    }
+    } else {
-    else if (temp_sr1 & I2C_SR1_BERR)
+      // Check both TxE/BTF == 1 before generating stop
-    {
+      while (!(s->SR1 && I2C_SR1_TXE));    // Check TxE
-      // Bus error
+      while (!(s->SR1 && I2C_SR1_BTF));    // Check BTF
-      s->SR1 &= ~(I2C_SR1_BERR); // Clear BERR
+      // No more data to send/receive. Initiate a STOP condition and finish
-      I2C_sendStop(); // Clear the bus
+      I2C_sendStop();
-      transactionState = TS_IDLE;
-      completionStatus = I2C_STATUS_BUS_ERROR;
       state = I2C_STATE_COMPLETED;
     }
-  } 
+  } else if (s->SR1 && I2C_SR1_RXNE) {
-  else {
+    // Master read completed without errors
-    // No error flags, so process event according to current state.
+    if (bytesToReceive == 1) {
-    switch (transactionState) {
+//      s->I2CM.CTRLB.bit.ACKACT = 1;  // NAK final byte
-      case TS_START:
+      I2C_sendStop();  // send stop
-        if (temp_sr1 & I2C_SR1_SB) {
+      receiveBuffer[rxCount++] = s->DR;  // Store received byte
-          // Event EV5
+      bytesToReceive = 0;
-          // Start bit has been sent successfully and we have the bus.
+      state = I2C_STATE_COMPLETED;
-          // If anything to send, initiate write.  Otherwise initiate read.
+    } else if (bytesToReceive) {
-          if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend)) {
+//      s->I2CM.CTRLB.bit.ACKACT = 0;  // ACK all but final byte
-            // Send address with read flag (1) or'd in
+      receiveBuffer[rxCount++] = s->DR;  // Store received byte
-            s->DR = (deviceAddress << 1) | 1;  //  send the address
+      bytesToReceive--;
-            transactionState = TS_R_ADDR;
-          } else {
-            // Send address with write flag (0) or'd in
-            s->DR = (deviceAddress << 1) | 0;  //  send the address
-            transactionState = TS_W_ADDR;
-          }
-        }
-        // SB bit is cleared by writing to DR (already done).
-        break;
-
-      case TS_W_ADDR:
-        if (temp_sr1 & I2C_SR1_ADDR) {
-          temp_sr2 = s->SR2; // read SR2 to complete clearing the ADDR bit
-          // Event EV6
-          // Address sent successfully, device has ack'd in response.
-          if (!bytesToSend) {
-            I2C_sendStop();
-            transactionState = TS_IDLE;
-            completionStatus = I2C_STATUS_OK;
-            state = I2C_STATE_COMPLETED;
-          } else {
-            // Put one byte into DR to load shift register.
-            s->DR = sendBuffer[txCount++];
-            bytesToSend--;
-            if (bytesToSend) {
-              // Put another byte to load DR
-              s->DR = sendBuffer[txCount++];
-              bytesToSend--;
-            }
-            if (!bytesToSend) {
-              // No more bytes to send.
-              // The TXE interrupt occurs when the DR is empty, and the BTF interrupt 
-              // occurs when the shift register is also empty (one character later).
-              // To avoid repeated TXE interrupts during this time, we disable TXE interrupt.
-              s->CR2 &= ~I2C_CR2_ITBUFEN;  // Wait for BTF interrupt, disable TXE interrupt
-              transactionState = TS_W_STOP;
-            } else {
-              // More data remaining to send after this interrupt, enable TXE interrupt.
-              s->CR2 |= I2C_CR2_ITBUFEN;
-              transactionState = TS_W_DATA;
-            }
-          }
-        }
-        break;
-
-      case TS_W_DATA:
-        if (temp_sr1 & I2C_SR1_TXE) {
-          // Event EV8_1/EV8
-          // Transmitter empty, write a byte to it.
-          if (bytesToSend) {
-            s->DR = sendBuffer[txCount++];
-            bytesToSend--;
-            if (!bytesToSend) {
-              s->CR2 &= ~I2C_CR2_ITBUFEN;  // Disable TXE interrupt
-              transactionState = TS_W_STOP;
-            }
-          }
-        } 
-        break;
-
-      case TS_W_STOP:
-        if (temp_sr1 & I2C_SR1_BTF) {
-          // Event EV8_2
-          // Done, last character sent. Anything to receive?
-          if (bytesToReceive) {
-            I2C_sendStart();
-            // NOTE: Three redundant BTF interrupts take place between the
-            // first BTF interrupt and the START interrupt.  I've tried all sorts
-            // of ways to eliminate them, and the only thing that worked for
-            // me was to loop until the BTF bit becomes reset.  Either way,
-            // it's a waste of processor time.  Anyone got a solution?
-            //while (s->SR1 && I2C_SR1_BTF) {}
-            transactionState = TS_START;
-          } else {
-            I2C_sendStop();
-            transactionState = TS_IDLE;
-            completionStatus = I2C_STATUS_OK;
-            state = I2C_STATE_COMPLETED;
-          }
-          s->SR1 &= I2C_SR1_BTF;  // Clear BTF interrupt
-        }
-        break;
-
-      case TS_R_ADDR:
-        if (temp_sr1 & I2C_SR1_ADDR) {
-          // Event EV6
-          // Address sent for receive.
-          // The next bit is different depending on whether there are 
-          // 1 byte, 2 bytes or >2 bytes to be received, in accordance with the
-          // Programmers Reference RM0390.
-          if (bytesToReceive == 1) {
-            // Receive 1 byte
-            s->CR1 &= ~I2C_CR1_ACK;  // Disable ack
-            temp_sr2 = s->SR2; // read SR2 to complete clearing the ADDR bit
-            // Next step will occur after a RXNE interrupt, so enable it
-            s->CR2 |= I2C_CR2_ITBUFEN;
-            transactionState = TS_R_STOP;
-          } else if (bytesToReceive == 2) {
-            // Receive 2 bytes
-            s->CR1 &= ~I2C_CR1_ACK;  // Disable ACK for final byte
-            s->CR1 |= I2C_CR1_POS;  // set POS flag to delay effect of ACK flag
-            // Next step will occur after a BTF interrupt, so disable RXNE interrupt
-            s->CR2 &= ~I2C_CR2_ITBUFEN;
-            temp_sr2 = s->SR2; // read SR2 to complete clearing the ADDR bit
-            transactionState = TS_R_STOP;
-          } else {
-            // >2 bytes, just wait for bytes to come in and ack them for the time being
-            // (ack flag has already been set).
-            // Next step will occur after a BTF interrupt, so disable RXNE interrupt
-            s->CR2 &= ~I2C_CR2_ITBUFEN;
-            temp_sr2 = s->SR2; // read SR2 to complete clearing the ADDR bit
-            transactionState = TS_R_DATA;
-          }
-        }
-        break;
-      
-      case TS_R_DATA:
-        // Event EV7/EV7_1
-        if (temp_sr1 & I2C_SR1_BTF) {
-          // Byte received in receiver - read next byte
-          if (bytesToReceive == 3) {
-            // Getting close to the last byte, so a specific sequence is recommended.
-            s->CR1 &= ~I2C_CR1_ACK;  // Reset ack for next byte received.
-            transactionState = TS_R_STOP;
-          }
-          receiveBuffer[rxCount++] = s->DR;  // Store received byte
-          bytesToReceive--;
-        } 
-        break;
-        
-      case TS_R_STOP:
-        if (temp_sr1 & I2C_SR1_BTF) {
-          // Event EV7 (last one)
-          // When we've got here, the receiver has got the last two bytes
-          // (or one byte, if only one byte is being received),
-          // and NAK has already been sent, so we need to read from the receiver.
-          if (bytesToReceive) {
-            if (bytesToReceive > 1) 
-              I2C_sendStop();
-            while(bytesToReceive) {
-              receiveBuffer[rxCount++] = s->DR;  // Store received byte(s)
-              bytesToReceive--;
-            }
-            // Finish.
-            transactionState = TS_IDLE;
-            completionStatus = I2C_STATUS_OK;
-            state = I2C_STATE_COMPLETED;
-          }
-        } else if (temp_sr1 & I2C_SR1_RXNE) {
-          if (bytesToReceive == 1) {
-            // One byte on a single-byte transfer.  Ack has already been set.
-            I2C_sendStop();
-            receiveBuffer[rxCount++] = s->DR; // Store received byte
-            bytesToReceive--;
-            // Finish.
-            transactionState = TS_IDLE;
-            completionStatus = I2C_STATUS_OK;
-            state = I2C_STATE_COMPLETED;
-          } else
-            s->SR1 &= I2C_SR1_RXNE;  // Acknowledge interrupt
-        }
-        break;
     }
-    // If we've received an interrupt at any other time, we're not interested so clear it
-    // to prevent it recurring ad infinitum.
-    s->SR1 = 0;
   }
-  
 }
 
 #endif /* I2CMANAGER_STM32_H */

defines.h

@@ -144,9 +144,9 @@
     #define DISABLE_EEPROM
   #endif
   // STM32 support for native I2C is awaiting development 
-  // #ifndef I2C_USE_WIRE
+  #ifndef I2C_USE_WIRE
-  // #define I2C_USE_WIRE
+  #define I2C_USE_WIRE
-  // #endif
+  #endif
 
 /* TODO when ready 
 #elif defined(ARDUINO_ARCH_RP2040)

version.h

@@ -3,8 +3,7 @@
 
 #include "StringFormatter.h"
 
-#define VERSION "5.1.6"
+#define VERSION "5.1.5"
-// 5.1.6  - STM32F4xx native I2C driver added
 // 5.1.5  - Added turntable object and EXRAIL commands
 //        - <I ...>, <JO ...>, <JP ...> - turntable commands
 //        - DCC_TURNTABLE, EXTT_TURNTABLE, IFTTPOSITION, ONROTATE, ROTATE, ROTATE_DCC, TT_ADDPOSITION, WAITFORTT EXRAIL