mirror of
https://github.com/DCC-EX/CommandStation-EX.git
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312 lines
13 KiB
C
312 lines
13 KiB
C
/*
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* © 2022-23 Paul M Antoine
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* © 2023, Neil McKechnie
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* All rights reserved.
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*
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* This file is part of CommandStation-EX
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*
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* This is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* It is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with CommandStation. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef I2CMANAGER_STM32_H
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#define I2CMANAGER_STM32_H
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#include <Arduino.h>
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#include "I2CManager.h"
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//#include <avr/io.h>
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//#include <avr/interrupt.h>
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#include <wiring_private.h>
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/***************************************************************************
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* Interrupt handler.
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* IRQ handler for SERCOM3 which is the default I2C definition for Arduino Zero
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* compatible variants such as the Sparkfun SAMD21 Dev Breakout etc.
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* Later we may wish to allow use of an alternate I2C bus, or more than one I2C
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* bus on the SAMD architecture
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***************************************************************************/
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#if defined(I2C_USE_INTERRUPTS) && defined(ARDUINO_ARCH_STM32)
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void I2C1_IRQHandler() {
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I2CManager.handleInterrupt();
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}
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#endif
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// Assume I2C1 for now - default I2C bus on Nucleo-F411RE and likely Nucleo-64 variants
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I2C_TypeDef *s = I2C1;
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#define I2C_IRQn I2C1_EV_IRQn
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#define I2C_BUSFREQ 16
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// I2C SR1 Status Register #1 bit definitions for convenience
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// #define I2C_SR1_SMBALERT (1<<15) // SMBus alert
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// #define I2C_SR1_TIMEOUT (1<<14) // Timeout of Tlow error
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// #define I2C_SR1_PECERR (1<<12) // PEC error in reception
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// #define I2C_SR1_OVR (1<<11) // Overrun/Underrun error
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// #define I2C_SR1_AF (1<<10) // Acknowledge failure
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// #define I2C_SR1_ARLO (1<<9) // Arbitration lost (master mode)
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// #define I2C_SR1_BERR (1<<8) // Bus error (misplaced start or stop condition)
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// #define I2C_SR1_TxE (1<<7) // Data register empty on transmit
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// #define I2C_SR1_RxNE (1<<6) // Data register not empty on receive
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// #define I2C_SR1_STOPF (1<<4) // Stop detection (slave mode)
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// #define I2C_SR1_ADD10 (1<<3) // 10 bit header sent
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// #define I2C_SR1_BTF (1<<2) // Byte transfer finished - data transfer done
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// #define I2C_SR1_ADDR (1<<1) // Address sent (master) or matched (slave)
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// #define I2C_SR1_SB (1<<0) // Start bit (master mode) 1=start condition generated
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// I2C CR1 Control Register #1 bit definitions for convenience
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// #define I2C_CR1_SWRST (1<<15) // Software reset - places peripheral under reset
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// #define I2C_CR1_ALERT (1<<13) // SMBus alert assertion
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// #define I2C_CR1_PEC (1<<12) // Packet Error Checking transfer in progress
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// #define I2C_CR1_POS (1<<11) // Acknowledge/PEC Postion (for data reception in PEC mode)
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// #define I2C_CR1_ACK (1<<10) // Acknowledge enable - ACK returned after byte is received (address or data)
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// #define I2C_CR1_STOP (1<<9) // STOP generated
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// #define I2C_CR1_START (1<<8) // START generated
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// #define I2C_CR1_NOSTRETCH (1<<7) // Clock stretching disable (slave mode)
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// #define I2C_CR1_ENGC (1<<6) // General call (broadcast) enable (address 00h is ACKed)
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// #define I2C_CR1_ENPEC (1<<5) // PEC Enable
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// #define I2C_CR1_ENARP (1<<4) // ARP enable (SMBus)
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// #define I2C_CR1_SMBTYPE (1<<3) // SMBus type, 1=host, 0=device
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// #define I2C_CR1_SMBUS (1<<1) // SMBus mode, 1=SMBus, 0=I2C
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// #define I2C_CR1_PE (1<<0) // I2C Peripheral enable
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/***************************************************************************
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* Set I2C clock speed register. This should only be called outside of
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* a transmission. The I2CManagerClass::_setClock() function ensures
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* that it is only called at the beginning of an I2C transaction.
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***************************************************************************/
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void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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// Calculate a rise time appropriate to the requested bus speed
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// Use 10x the rise time spec to enable integer divide of 62.5ns clock period
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uint16_t t_rise;
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uint32_t ccr_freq;
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if (i2cClockSpeed < 200000L) {
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// i2cClockSpeed = 100000L;
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t_rise = 0x11; // (1000ns /62.5ns) + 1;
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}
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else if (i2cClockSpeed < 800000L)
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{
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i2cClockSpeed = 400000L;
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t_rise = 0x06; // (300ns / 62.5ns) + 1;
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// } else if (i2cClockSpeed < 1200000L) {
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// i2cClockSpeed = 1000000L;
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// t_rise = 120;
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}
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else
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{
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i2cClockSpeed = 100000L;
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t_rise = 0x11; // (1000ns /62.5ns) + 1;
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}
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// Enable the I2C master mode
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s->CR1 &= ~(I2C_CR1_PE); // Enable I2C
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// Software reset the I2C peripheral
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// s->CR1 |= I2C_CR1_SWRST; // reset the I2C
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// Release reset
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// s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
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// Calculate baudrate - using a rise time appropriate for the speed
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ccr_freq = I2C_BUSFREQ * 1000000 / i2cClockSpeed / 2;
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// Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
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// Bit 14: Duty, fast mode duty cycle
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// Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns, so CCR divisor must be 0x50 (80 * 62.5ns = 5000ns)
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s->CCR = (uint16_t)ccr_freq;
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// Configure the rise time register
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s->TRISE = t_rise; // 1000 ns / 62.5 ns = 16 + 1
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// Enable the I2C master mode
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s->CR1 |= I2C_CR1_PE; // Enable I2C
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}
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/***************************************************************************
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* Initialise I2C registers.
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***************************************************************************/
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void I2CManagerClass::I2C_init()
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{
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//Setting up the clocks
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RCC->APB1ENR |= (1<<21); // Enable I2C CLOCK
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RCC->AHB1ENR |= (1<<1); // Enable GPIOB CLOCK for PB8/PB9
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// Standard I2C pins are SCL on PB8 and SDA on PB9
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// Bits (17:16)= 1:0 --> Alternate Function for Pin PB8;
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// Bits (19:18)= 1:0 --> Alternate Function for Pin PB9
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GPIOB->MODER |= (2<<(8*2)) | (2<<(9*2)); // PB8 and PB9 set to ALT function
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GPIOB->OTYPER |= (1<<8) | (1<<9); // PB8 and PB9 set to open drain output capability
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GPIOB->OSPEEDR |= (3<<(8*2)) | (3<<(9*2)); // PB8 and PB9 set to High Speed mode
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GPIOB->PUPDR |= (1<<(8*2)) | (1<<(9*2)); // PB8 and PB9 set to pull-up capability
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// Alt Function High register routing pins PB8 and PB9 for I2C1:
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// Bits (3:2:1:0) = 0:1:0:0 --> AF4 for pin PB8
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// Bits (7:6:5:4) = 0:1:0:0 --> AF4 for pin PB9
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GPIOB->AFR[1] |= (4<<0) | (4<<4); // PB8 on low nibble, PB9 on next nibble up
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// Software reset the I2C peripheral
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s->CR1 |= I2C_CR1_SWRST; // reset the I2C
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s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
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// Program the peripheral input clock in CR2 Register in order to generate correct timings
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s->CR2 |= I2C_BUSFREQ; // PCLK1 FREQUENCY in MHz
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#if defined(I2C_USE_INTERRUPTS)
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// Setting NVIC
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NVIC_SetPriority(I2C_IRQn, 1); // Match default priorities
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NVIC_EnableIRQ(I2C_IRQn);
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// CR2 Interrupt Settings
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// Bit 15-13: reserved
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// Bit 12: LAST - DMA last transfer
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// Bit 11: DMAEN - DMA enable
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// Bit 10: ITBUFEN - Buffer interrupt enable
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// Bit 9: ITEVTEN - Event interrupt enable
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// Bit 8: ITERREN - Error interrupt enable
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// Bit 7-6: reserved
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// Bit 5-0: FREQ - Peripheral clock frequency (max 50MHz)
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// s->CR2 |= 0x0700; // Enable Buffer, Event and Error interrupts
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s->CR2 |= 0x0300; // Enable Event and Error interrupts
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#endif
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// Calculate baudrate and set default rate for now
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// Configure the Clock Control Register for 100KHz SCL frequency
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// Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
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// Bit 14: Duty, fast mode duty cycle
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// Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns, so CCR divisor must be 0x50 (80 * 62.5ns = 5000ns)
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s->CCR = 0x0050;
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// Configure the rise time register - max allowed in 1000ns
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s->TRISE = 0x0011; // 1000 ns / 62.5 ns = 16 + 1
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// Enable the I2C master mode
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s->CR1 |= I2C_CR1_PE; // Enable I2C
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// Setting bus idle mode and wait for sync
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}
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/***************************************************************************
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* Initiate a start bit for transmission.
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***************************************************************************/
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void I2CManagerClass::I2C_sendStart() {
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// Set counters here in case this is a retry.
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rxCount = txCount = 0;
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uint8_t temp;
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// On a single-master I2C bus, the start bit won't be sent until the bus
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// state goes to IDLE so we can request it without waiting. On a
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// multi-master bus, the bus may be BUSY under control of another master,
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// in which case we can avoid some arbitration failures by waiting until
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// the bus state is IDLE. We don't do that here.
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// If anything to send, initiate write. Otherwise initiate read.
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if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
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{
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// Send start for read operation
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s->CR1 |= I2C_CR1_ACK; // Enable the ACK
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s->CR1 |= I2C_CR1_START; // Generate START
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// Send address with read flag (1) or'd in
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s->DR = (deviceAddress << 1) | 1; // send the address
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while (!(s->SR1 && I2C_SR1_ADDR)); // wait for ADDR bit to set
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// Special case for 1 byte reads!
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if (bytesToReceive == 1)
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{
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s->CR1 &= ~I2C_CR1_ACK; // clear the ACK bit
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temp = I2C1->SR1 | I2C1->SR2; // read SR1 and SR2 to clear the ADDR bit.... EV6 condition
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s->CR1 |= I2C_CR1_STOP; // Stop I2C
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}
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else
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temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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else {
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// Send start for write operation
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s->CR1 |= I2C_CR1_ACK; // Enable the ACK
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s->CR1 |= I2C_CR1_START; // Generate START
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// Send address with write flag (0) or'd in
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s->DR = (deviceAddress << 1) | 0; // send the address
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while (!(s->SR1 && I2C_SR1_ADDR)); // wait for ADDR bit to set
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temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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}
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/***************************************************************************
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* Initiate a stop bit for transmission (does not interrupt)
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***************************************************************************/
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void I2CManagerClass::I2C_sendStop() {
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s->CR1 |= I2C_CR1_STOP; // Stop I2C
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}
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/***************************************************************************
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* Close I2C down
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***************************************************************************/
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void I2CManagerClass::I2C_close() {
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I2C_sendStop();
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// Disable the I2C master mode and wait for sync
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s->CR1 &= ~I2C_CR1_PE; // Disable I2C peripheral
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// Should never happen, but wait for up to 500us only.
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unsigned long startTime = micros();
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while ((s->CR1 && I2C_CR1_PE) != 0) {
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if (micros() - startTime >= 500UL) break;
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}
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}
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/***************************************************************************
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* Main state machine for I2C, called from interrupt handler or,
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* if I2C_USE_INTERRUPTS isn't defined, from the I2CManagerClass::loop() function
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* (and therefore, indirectly, from I2CRB::wait() and I2CRB::isBusy()).
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***************************************************************************/
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void I2CManagerClass::I2C_handleInterrupt() {
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if (s->SR1 && I2C_SR1_ARLO) {
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// Arbitration lost, restart
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I2C_sendStart(); // Reinitiate request
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} else if (s->SR1 && I2C_SR1_BERR) {
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// Bus error
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completionStatus = I2C_STATUS_BUS_ERROR;
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state = I2C_STATE_COMPLETED;
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} else if (s->SR1 && I2C_SR1_TXE) {
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// Master write completed
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if (s->SR1 && (1<<10)) {
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// Nacked, send stop.
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I2C_sendStop();
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completionStatus = I2C_STATUS_NEGATIVE_ACKNOWLEDGE;
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state = I2C_STATE_COMPLETED;
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} else if (bytesToSend) {
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// Acked, so send next byte
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s->DR = sendBuffer[txCount++];
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bytesToSend--;
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} else if (bytesToReceive) {
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// Last sent byte acked and no more to send. Send repeated start, address and read bit.
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// s->I2CM.ADDR.bit.ADDR = (deviceAddress << 1) | 1;
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} else {
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// Check both TxE/BTF == 1 before generating stop
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while (!(s->SR1 && I2C_SR1_TXE)); // Check TxE
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while (!(s->SR1 && I2C_SR1_BTF)); // Check BTF
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// No more data to send/receive. Initiate a STOP condition and finish
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I2C_sendStop();
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state = I2C_STATE_COMPLETED;
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}
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} else if (s->SR1 && I2C_SR1_RXNE) {
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// Master read completed without errors
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if (bytesToReceive == 1) {
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// s->I2CM.CTRLB.bit.ACKACT = 1; // NAK final byte
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I2C_sendStop(); // send stop
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receiveBuffer[rxCount++] = s->DR; // Store received byte
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bytesToReceive = 0;
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state = I2C_STATE_COMPLETED;
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} else if (bytesToReceive) {
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// s->I2CM.CTRLB.bit.ACKACT = 0; // ACK all but final byte
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receiveBuffer[rxCount++] = s->DR; // Store received byte
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bytesToReceive--;
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}
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}
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}
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#endif /* I2CMANAGER_STM32_H */
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