mirror of
https://github.com/DCC-EX/CommandStation-EX.git
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80472a76dc
Previously the driver allowed speeds down to 32kHz but lower speeds were not implemented correctly.
210 lines
8.7 KiB
C
210 lines
8.7 KiB
C
/*
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* © 2021, Neil McKechnie. All rights reserved.
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*
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* This file is part of CommandStation-EX
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*
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* This is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* It is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with CommandStation. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef I2CMANAGER_AVR_H
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#define I2CMANAGER_AVR_H
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#include <Arduino.h>
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#include "I2CManager.h"
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#include <avr/io.h>
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#include <avr/interrupt.h>
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/****************************************************************************
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TWI State codes
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****************************************************************************/
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// General TWI Master staus codes
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#define TWI_START 0x08 // START has been transmitted
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#define TWI_REP_START 0x10 // Repeated START has been transmitted
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#define TWI_ARB_LOST 0x38 // Arbitration lost
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// TWI Master Transmitter staus codes
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#define TWI_MTX_ADR_ACK 0x18 // SLA+W has been tramsmitted and ACK received
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#define TWI_MTX_ADR_NACK 0x20 // SLA+W has been tramsmitted and NACK received
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#define TWI_MTX_DATA_ACK 0x28 // Data byte has been tramsmitted and ACK received
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#define TWI_MTX_DATA_NACK 0x30 // Data byte has been tramsmitted and NACK received
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// TWI Master Receiver staus codes
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#define TWI_MRX_ADR_ACK 0x40 // SLA+R has been tramsmitted and ACK received
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#define TWI_MRX_ADR_NACK 0x48 // SLA+R has been tramsmitted and NACK received
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#define TWI_MRX_DATA_ACK 0x50 // Data byte has been received and ACK tramsmitted
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#define TWI_MRX_DATA_NACK 0x58 // Data byte has been received and NACK tramsmitted
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// TWI Miscellaneous status codes
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#define TWI_NO_STATE 0xF8 // No relevant state information available
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#define TWI_BUS_ERROR 0x00 // Bus error due to an illegal START or STOP condition
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#define TWI_TWBR ((F_CPU / I2C_FREQ) - 16) / 2 // TWI Bit rate Register setting.
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#if defined(I2C_USE_INTERRUPTS)
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#define ENABLE_TWI_INTERRUPT (1<<TWIE)
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#else
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#define ENABLE_TWI_INTERRUPT 0
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#endif
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/***************************************************************************
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* Set I2C clock speed register.
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***************************************************************************/
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void I2CManagerClass::I2C_setClock(unsigned long i2cClockSpeed) {
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unsigned long temp = ((F_CPU / i2cClockSpeed) - 16) / 2;
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for (uint8_t preScaler = 0; preScaler<=3; preScaler++) {
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if (temp <= 255) {
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TWBR = temp;
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TWSR = (TWSR & 0xfc) | preScaler;
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return;
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} else
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temp /= 4;
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}
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// Set slowest speed ~= 500 bits/sec
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TWBR = 255;
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TWSR |= 0x03;
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}
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/***************************************************************************
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* Initialise I2C registers.
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***************************************************************************/
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void I2CManagerClass::I2C_init()
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{
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TWSR = 0;
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TWBR = TWI_TWBR; // Set bit rate register (Baudrate). Defined in header file.
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TWDR = 0xFF; // Default content = SDA released.
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TWCR = (1<<TWINT); // Clear interrupt flag
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pinMode(SDA, INPUT_PULLUP);
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pinMode(SCL, INPUT_PULLUP);
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}
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/***************************************************************************
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* Initiate a start bit for transmission.
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***************************************************************************/
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void I2CManagerClass::I2C_sendStart() {
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bytesToSend = currentRequest->writeLen;
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bytesToReceive = currentRequest->readLen;
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// We may have initiated a stop bit before this without waiting for it.
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// Wait for stop bit to be sent before sending start.
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while (TWCR & (1<<TWSTO)) {}
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TWCR = (1<<TWEN)|ENABLE_TWI_INTERRUPT|(1<<TWINT)|(1<<TWEA)|(1<<TWSTA); // Send Start
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}
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/***************************************************************************
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* Initiate a stop bit for transmission (does not interrupt)
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***************************************************************************/
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void I2CManagerClass::I2C_sendStop() {
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TWDR = 0xff; // Default condition = SDA released
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TWCR = (1<<TWEN)|(1<<TWINT)|(1<<TWEA)|(1<<TWSTO); // Send Stop
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}
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/***************************************************************************
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* Close I2C down
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***************************************************************************/
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void I2CManagerClass::I2C_close() {
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// disable TWI
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I2C_sendStop();
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while (TWCR & (1<<TWSTO)) {}
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TWCR = (1<<TWINT); // clear any interrupt and stop twi.
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}
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/***************************************************************************
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* Main state machine for I2C, called from interrupt handler or,
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* if I2C_USE_INTERRUPTS isn't defined, from the I2CManagerClass::loop() function
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* (and therefore, indirectly, from I2CRB::wait() and I2CRB::isBusy()).
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***************************************************************************/
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void I2CManagerClass::I2C_handleInterrupt() {
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if (!(TWCR & (1<<TWINT))) return; // Nothing to do.
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uint8_t twsr = TWSR & 0xF8;
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// Cases are ordered so that the most frequently used ones are tested first.
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switch (twsr) {
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case TWI_MTX_DATA_ACK: // Data byte has been transmitted and ACK received
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case TWI_MTX_ADR_ACK: // SLA+W has been transmitted and ACK received
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if (bytesToSend) { // Send first.
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if (operation == OPERATION_SEND_P)
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TWDR = GETFLASH(currentRequest->writeBuffer + (txCount++));
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else
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TWDR = currentRequest->writeBuffer[txCount++];
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bytesToSend--;
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TWCR = (1<<TWEN)|ENABLE_TWI_INTERRUPT|(1<<TWINT)|(1<<TWEA);
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} else if (bytesToReceive) { // All sent, anything to receive?
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while (TWCR & (1<<TWSTO)) {} // Wait for stop to be sent
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TWCR = (1<<TWEN)|ENABLE_TWI_INTERRUPT|(1<<TWINT)|(1<<TWEA)|(1<<TWSTA); // Send Start
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} else { // Nothing left to send or receive
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TWDR = 0xff; // Default condition = SDA released
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TWCR = (1<<TWEN)|(1<<TWINT)|(1<<TWEA)|(1<<TWSTO); // Send Stop
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state = I2C_STATUS_OK;
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}
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break;
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case TWI_MRX_DATA_ACK: // Data byte has been received and ACK transmitted
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if (bytesToReceive > 0) {
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currentRequest->readBuffer[rxCount++] = TWDR;
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bytesToReceive--;
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}
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/* fallthrough */
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case TWI_MRX_ADR_ACK: // SLA+R has been sent and ACK received
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if (bytesToReceive <= 1) {
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TWCR = (1<<TWEN)|ENABLE_TWI_INTERRUPT|(1<<TWINT); // Send NACK after next reception
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} else {
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// send ack
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TWCR = (1<<TWEN)|ENABLE_TWI_INTERRUPT|(1<<TWINT)|(1<<TWEA);
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}
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break;
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case TWI_MRX_DATA_NACK: // Data byte has been received and NACK transmitted
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if (bytesToReceive > 0) {
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currentRequest->readBuffer[rxCount++] = TWDR;
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bytesToReceive--;
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}
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TWCR = (1<<TWEN)|(1<<TWINT)|(1<<TWEA)|(1<<TWSTO); // Send Stop
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state = I2C_STATUS_OK;
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break;
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case TWI_START: // START has been transmitted
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case TWI_REP_START: // Repeated START has been transmitted
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// Set up address and R/W
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if (operation == OPERATION_READ || (operation==OPERATION_REQUEST && !bytesToSend))
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TWDR = (currentRequest->i2cAddress << 1) | 1; // SLA+R
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else
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TWDR = (currentRequest->i2cAddress << 1) | 0; // SLA+W
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TWCR = (1<<TWEN)|ENABLE_TWI_INTERRUPT|(1<<TWINT)|(1<<TWEA);
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break;
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case TWI_MTX_ADR_NACK: // SLA+W has been transmitted and NACK received
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case TWI_MRX_ADR_NACK: // SLA+R has been transmitted and NACK received
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case TWI_MTX_DATA_NACK: // Data byte has been transmitted and NACK received
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TWDR = 0xff; // Default condition = SDA released
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TWCR = (1<<TWEN)|(1<<TWINT)|(1<<TWEA)|(1<<TWSTO); // Send Stop
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state = I2C_STATUS_NEGATIVE_ACKNOWLEDGE;
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break;
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case TWI_ARB_LOST: // Arbitration lost
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// Restart transaction from start.
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I2C_sendStart();
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break;
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case TWI_BUS_ERROR: // Bus error due to an illegal START or STOP condition
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default:
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TWDR = 0xff; // Default condition = SDA released
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TWCR = (1<<TWEN)|(1<<TWINT)|(1<<TWEA)|(1<<TWSTO); // Send Stop
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state = I2C_STATUS_TRANSMIT_ERROR;
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}
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}
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#if defined(I2C_USE_INTERRUPTS)
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ISR(TWI_vect) {
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I2CManagerClass::handleInterrupt();
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}
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#endif
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#endif /* I2CMANAGER_AVR_H */
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