mirror of
https://github.com/DCC-EX/CommandStation-EX.git
synced 2024-11-23 08:06:13 +01:00
248 lines
9.5 KiB
C
248 lines
9.5 KiB
C
/*
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* © 2022 Paul M Antoine
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* © 2023, Neil McKechnie
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* All rights reserved.
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*
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* This file is part of CommandStation-EX
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*
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* This is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* It is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with CommandStation. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef I2CMANAGER_SAMD_H
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#define I2CMANAGER_SAMD_H
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#include <Arduino.h>
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#include "I2CManager.h"
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//#include <avr/io.h>
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//#include <avr/interrupt.h>
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#include <wiring_private.h>
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/***************************************************************************
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* Interrupt handler.
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* IRQ handler for SERCOM3 which is the default I2C definition for Arduino Zero
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* compatible variants such as the Sparkfun SAMD21 Dev Breakout etc.
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* Later we may wish to allow use of an alternate I2C bus, or more than one I2C
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* bus on the SAMD architecture
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***************************************************************************/
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#if defined(I2C_USE_INTERRUPTS) && defined(ARDUINO_SAMD_ZERO)
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void SERCOM3_Handler() {
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I2CManager.handleInterrupt();
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}
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#endif
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// Assume SERCOM3 for now - default I2C bus on Arduino Zero and variants of same
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Sercom *s = SERCOM3;
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/***************************************************************************
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* Set I2C clock speed register. This should only be called outside of
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* a transmission. The I2CManagerClass::_setClock() function ensures
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* that it is only called at the beginning of an I2C transaction.
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***************************************************************************/
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void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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// Calculate a rise time appropriate to the requested bus speed
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int t_rise;
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if (i2cClockSpeed < 200000L) {
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i2cClockSpeed = 100000L; // NB: this overrides a "force clock" of lower than 100KHz!
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t_rise = 1000;
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} else if (i2cClockSpeed < 800000L) {
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i2cClockSpeed = 400000L;
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t_rise = 300;
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} else if (i2cClockSpeed < 1200000L) {
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i2cClockSpeed = 1000000L;
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t_rise = 120;
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} else {
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i2cClockSpeed = 100000L;
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t_rise = 1000;
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}
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// Wait while the bus is busy
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while (s->I2CM.STATUS.bit.BUSSTATE != 0x1);
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// Disable the I2C master mode and wait for sync
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s->I2CM.CTRLA.bit.ENABLE = 0 ;
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while (s->I2CM.SYNCBUSY.bit.ENABLE != 0);
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// Calculate baudrate - using a rise time appropriate for the speed
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s->I2CM.BAUD.bit.BAUD = SystemCoreClock / (2 * i2cClockSpeed) - 5 - (((SystemCoreClock / 1000000) * t_rise) / (2 * 1000));
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// Enable the I2C master mode and wait for sync
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s->I2CM.CTRLA.bit.ENABLE = 1 ;
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while (s->I2CM.SYNCBUSY.bit.ENABLE != 0);
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// Setting bus idle mode and wait for sync
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s->I2CM.STATUS.bit.BUSSTATE = 1 ;
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while (s->I2CM.SYNCBUSY.bit.SYSOP != 0);
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}
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/***************************************************************************
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* Initialise I2C registers.
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***************************************************************************/
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void I2CManagerClass::I2C_init()
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{
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//Setting clock
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCM_SERCOM3_CORE) | // Generic Clock 0 (SERCOM3)
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GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
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GCLK_CLKCTRL_CLKEN ;
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/* Wait for peripheral clock synchronization */
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY );
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// Software reset the SERCOM
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s->I2CM.CTRLA.bit.SWRST = 1;
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//Wait both bits Software Reset from CTRLA and SYNCBUSY are equal to 0
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while(s->I2CM.CTRLA.bit.SWRST || s->I2CM.SYNCBUSY.bit.SWRST);
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// Set master mode and enable SCL Clock Stretch mode (stretch after ACK bit)
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s->I2CM.CTRLA.reg = SERCOM_I2CM_CTRLA_MODE( I2C_MASTER_OPERATION )/* |
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SERCOM_I2CM_CTRLA_SCLSM*/ ;
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// Enable Smart mode (but not Quick Command)
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s->I2CM.CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
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#if defined(I2C_USE_INTERRUPTS)
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// Setting NVIC
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NVIC_EnableIRQ(SERCOM3_IRQn);
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NVIC_SetPriority (SERCOM3_IRQn, SERCOM_NVIC_PRIORITY); // Match default SERCOM priorities
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// NVIC_SetPriority (SERCOM3_IRQn, 0); // Set highest priority
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// Enable all interrupts
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s->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB | SERCOM_I2CM_INTENSET_ERROR;
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#endif
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// Calculate baudrate and set default rate for now
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s->I2CM.BAUD.bit.BAUD = SystemCoreClock / ( 2 * I2C_FREQ) - 7 / (2 * 1000);
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// Enable the I2C master mode and wait for sync
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s->I2CM.CTRLA.bit.ENABLE = 1 ;
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while (s->I2CM.SYNCBUSY.bit.ENABLE != 0);
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// Setting bus idle mode and wait for sync
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s->I2CM.STATUS.bit.BUSSTATE = 1 ;
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while (s->I2CM.SYNCBUSY.bit.SYSOP != 0);
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// Set SDA/SCL pins as outputs and enable pullups, at present we assume these are
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// the default ones for SERCOM3 (see assumption above)
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pinPeripheral(PIN_WIRE_SDA, g_APinDescription[PIN_WIRE_SDA].ulPinType);
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pinPeripheral(PIN_WIRE_SCL, g_APinDescription[PIN_WIRE_SCL].ulPinType);
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// Enable the SCL and SDA pins on the sercom: includes increased driver strength,
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// pull-up resistors and pin multiplexer
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PORT->Group[g_APinDescription[PIN_WIRE_SCL].ulPort].PINCFG[g_APinDescription[PIN_WIRE_SCL].ulPin].reg =
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PORT_PINCFG_DRVSTR | PORT_PINCFG_PULLEN | PORT_PINCFG_PMUXEN;
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PORT->Group[g_APinDescription[PIN_WIRE_SDA].ulPort].PINCFG[g_APinDescription[PIN_WIRE_SDA].ulPin].reg =
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PORT_PINCFG_DRVSTR | PORT_PINCFG_PULLEN | PORT_PINCFG_PMUXEN;
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}
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/***************************************************************************
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* Initiate a start bit for transmission.
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***************************************************************************/
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void I2CManagerClass::I2C_sendStart() {
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// Set counters here in case this is a retry.
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txCount = 0;
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rxCount = 0;
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// On a single-master I2C bus, the start bit won't be sent until the bus
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// state goes to IDLE so we can request it without waiting. On a
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// multi-master bus, the bus may be BUSY under control of another master,
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// in which case we can avoid some arbitration failures by waiting until
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// the bus state is IDLE. We don't do that here.
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// If anything to send, initiate write. Otherwise initiate read.
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if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
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{
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// Send start and address with read flag (1) or'd in
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s->I2CM.ADDR.bit.ADDR = (deviceAddress << 1) | 1;
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}
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else {
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// Send start and address with write flag (0) or'd in
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s->I2CM.ADDR.bit.ADDR = (deviceAddress << 1ul) | 0;
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}
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}
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/***************************************************************************
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* Initiate a stop bit for transmission (does not interrupt)
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***************************************************************************/
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void I2CManagerClass::I2C_sendStop() {
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s->I2CM.CTRLB.bit.CMD = 3; // Stop condition
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}
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/***************************************************************************
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* Close I2C down
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***************************************************************************/
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void I2CManagerClass::I2C_close() {
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I2C_sendStop();
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// Disable the I2C master mode and wait for sync
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s->I2CM.CTRLA.bit.ENABLE = 0 ;
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// Wait for up to 500us only.
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unsigned long startTime = micros();
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while (s->I2CM.SYNCBUSY.bit.ENABLE != 0) {
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if (micros() - startTime >= 500UL) break;
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}
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}
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/***************************************************************************
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* Main state machine for I2C, called from interrupt handler or,
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* if I2C_USE_INTERRUPTS isn't defined, from the I2CManagerClass::loop() function
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* (and therefore, indirectly, from I2CRB::wait() and I2CRB::isBusy()).
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***************************************************************************/
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void I2CManagerClass::I2C_handleInterrupt() {
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if (s->I2CM.STATUS.bit.ARBLOST) {
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// Arbitration lost, restart
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I2C_sendStart(); // Reinitiate request
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} else if (s->I2CM.STATUS.bit.BUSERR) {
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// Bus error
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completionStatus = I2C_STATUS_BUS_ERROR;
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state = I2C_STATE_COMPLETED; // Completed with error
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} else if (s->I2CM.INTFLAG.bit.MB) {
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// Master write completed
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if (s->I2CM.STATUS.bit.RXNACK) {
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// Nacked, send stop.
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I2C_sendStop();
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completionStatus = I2C_STATUS_NEGATIVE_ACKNOWLEDGE;
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state = I2C_STATE_COMPLETED; // Completed with error
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} else if (bytesToSend) {
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// Acked, so send next byte
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s->I2CM.DATA.bit.DATA = sendBuffer[txCount++];
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bytesToSend--;
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} else if (bytesToReceive) {
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// Last sent byte acked and no more to send. Send repeated start, address and read bit.
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s->I2CM.ADDR.bit.ADDR = (deviceAddress << 1) | 1;
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} else {
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// No more data to send/receive. Initiate a STOP condition
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I2C_sendStop();
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state = I2C_STATE_COMPLETED; // Completed OK
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}
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} else if (s->I2CM.INTFLAG.bit.SB) {
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// Master read completed without errors
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if (bytesToReceive == 1) {
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s->I2CM.CTRLB.bit.ACKACT = 1; // NAK final byte
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I2C_sendStop(); // send stop
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receiveBuffer[rxCount++] = s->I2CM.DATA.bit.DATA; // Store received byte
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bytesToReceive = 0;
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state = I2C_STATE_COMPLETED; // Completed OK
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} else if (bytesToReceive) {
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s->I2CM.CTRLB.bit.ACKACT = 0; // ACK all but final byte
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receiveBuffer[rxCount++] = s->I2CM.DATA.bit.DATA; // Store received byte
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bytesToReceive--;
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}
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}
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}
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#endif /* I2CMANAGER_SAMD_H */
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