mirror of
https://github.com/DCC-EX/CommandStation-EX.git
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612 lines
19 KiB
C++
612 lines
19 KiB
C++
// Microchip ENC28J60 Ethernet Interface Driver
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// Author: Guido Socher
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// Copyright: GPL V2
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//
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// Based on the enc28j60.c file from the AVRlib library by Pascal Stang.
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// For AVRlib See http://www.procyonengineering.com/
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// Used with explicit permission of Pascal Stang.
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//
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// 2010-05-20 <jc@wippler.nl>
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#if ARDUINO >= 100
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#include <Arduino.h> // Arduino 1.0
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#else
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#include <Wprogram.h> // Arduino 0022
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#endif
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#include <SPI.h>
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#include "enc28j60.h"
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uint16_t ENC28J60::bufferSize;
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bool ENC28J60::broadcast_enabled = false;
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bool ENC28J60::promiscuous_enabled = false;
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// ENC28J60 Control Registers
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// Control register definitions are a combination of address,
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// bank number, and Ethernet/MAC/PHY indicator bits.
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// - Register address (bits 0-4)
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// - Bank number (bits 5-6)
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// - MAC/PHY indicator (bit 7)
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#define ADDR_MASK 0x1F
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#define BANK_MASK 0x60
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#define SPRD_MASK 0x80
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// All-bank registers
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#define EIE 0x1B
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#define EIR 0x1C
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#define ESTAT 0x1D
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#define ECON2 0x1E
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#define ECON1 0x1F
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// Bank 0 registers
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#define ERDPT (0x00|0x00)
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#define EWRPT (0x02|0x00)
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#define ETXST (0x04|0x00)
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#define ETXND (0x06|0x00)
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#define ERXST (0x08|0x00)
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#define ERXND (0x0A|0x00)
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#define ERXRDPT (0x0C|0x00)
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// #define ERXWRPT (0x0E|0x00)
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#define EDMAST (0x10|0x00)
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#define EDMAND (0x12|0x00)
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// #define EDMADST (0x14|0x00)
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#define EDMACS (0x16|0x00)
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// Bank 1 registers
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#define EHT0 (0x00|0x20)
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#define EHT1 (0x01|0x20)
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#define EHT2 (0x02|0x20)
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#define EHT3 (0x03|0x20)
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#define EHT4 (0x04|0x20)
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#define EHT5 (0x05|0x20)
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#define EHT6 (0x06|0x20)
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#define EHT7 (0x07|0x20)
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#define EPMM0 (0x08|0x20)
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#define EPMM1 (0x09|0x20)
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#define EPMM2 (0x0A|0x20)
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#define EPMM3 (0x0B|0x20)
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#define EPMM4 (0x0C|0x20)
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#define EPMM5 (0x0D|0x20)
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#define EPMM6 (0x0E|0x20)
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#define EPMM7 (0x0F|0x20)
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#define EPMCS (0x10|0x20)
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// #define EPMO (0x14|0x20)
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#define EWOLIE (0x16|0x20)
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#define EWOLIR (0x17|0x20)
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#define ERXFCON (0x18|0x20)
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#define EPKTCNT (0x19|0x20)
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// Bank 2 registers
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#define MACON1 (0x00|0x40|0x80)
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#define MACON3 (0x02|0x40|0x80)
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#define MACON4 (0x03|0x40|0x80)
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#define MABBIPG (0x04|0x40|0x80)
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#define MAIPG (0x06|0x40|0x80)
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#define MACLCON1 (0x08|0x40|0x80)
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#define MACLCON2 (0x09|0x40|0x80)
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#define MAMXFL (0x0A|0x40|0x80)
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#define MAPHSUP (0x0D|0x40|0x80)
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#define MICON (0x11|0x40|0x80)
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#define MICMD (0x12|0x40|0x80)
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#define MIREGADR (0x14|0x40|0x80)
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#define MIWR (0x16|0x40|0x80)
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#define MIRD (0x18|0x40|0x80)
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// Bank 3 registers
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#define MAADR1 (0x00|0x60|0x80)
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#define MAADR0 (0x01|0x60|0x80)
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#define MAADR3 (0x02|0x60|0x80)
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#define MAADR2 (0x03|0x60|0x80)
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#define MAADR5 (0x04|0x60|0x80)
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#define MAADR4 (0x05|0x60|0x80)
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#define EBSTSD (0x06|0x60)
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#define EBSTCON (0x07|0x60)
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#define EBSTCS (0x08|0x60)
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#define MISTAT (0x0A|0x60|0x80)
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#define EREVID (0x12|0x60)
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#define ECOCON (0x15|0x60)
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#define EFLOCON (0x17|0x60)
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#define EPAUS (0x18|0x60)
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// ENC28J60 ERXFCON Register Bit Definitions
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#define ERXFCON_UCEN 0x80
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#define ERXFCON_ANDOR 0x40
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#define ERXFCON_CRCEN 0x20
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#define ERXFCON_PMEN 0x10
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#define ERXFCON_MPEN 0x08
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#define ERXFCON_HTEN 0x04
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#define ERXFCON_MCEN 0x02
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#define ERXFCON_BCEN 0x01
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// ENC28J60 EIE Register Bit Definitions
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#define EIE_INTIE 0x80
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#define EIE_PKTIE 0x40
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#define EIE_DMAIE 0x20
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#define EIE_LINKIE 0x10
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#define EIE_TXIE 0x08
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#define EIE_WOLIE 0x04
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#define EIE_TXERIE 0x02
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#define EIE_RXERIE 0x01
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// ENC28J60 EIR Register Bit Definitions
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#define EIR_PKTIF 0x40
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#define EIR_DMAIF 0x20
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#define EIR_LINKIF 0x10
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#define EIR_TXIF 0x08
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#define EIR_WOLIF 0x04
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#define EIR_TXERIF 0x02
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#define EIR_RXERIF 0x01
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// ENC28J60 ESTAT Register Bit Definitions
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#define ESTAT_INT 0x80
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#define ESTAT_LATECOL 0x10
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#define ESTAT_RXBUSY 0x04
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#define ESTAT_TXABRT 0x02
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#define ESTAT_CLKRDY 0x01
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// ENC28J60 ECON2 Register Bit Definitions
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#define ECON2_AUTOINC 0x80
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#define ECON2_PKTDEC 0x40
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#define ECON2_PWRSV 0x20
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#define ECON2_VRPS 0x08
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// ENC28J60 ECON1 Register Bit Definitions
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#define ECON1_TXRST 0x80
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#define ECON1_RXRST 0x40
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#define ECON1_DMAST 0x20
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#define ECON1_CSUMEN 0x10
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#define ECON1_TXRTS 0x08
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#define ECON1_RXEN 0x04
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#define ECON1_BSEL1 0x02
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#define ECON1_BSEL0 0x01
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// ENC28J60 MACON1 Register Bit Definitions
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#define MACON1_LOOPBK 0x10
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#define MACON1_TXPAUS 0x08
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#define MACON1_RXPAUS 0x04
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#define MACON1_PASSALL 0x02
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#define MACON1_MARXEN 0x01
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// ENC28J60 MACON3 Register Bit Definitions
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#define MACON3_PADCFG2 0x80
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#define MACON3_PADCFG1 0x40
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#define MACON3_PADCFG0 0x20
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#define MACON3_TXCRCEN 0x10
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#define MACON3_PHDRLEN 0x08
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#define MACON3_HFRMLEN 0x04
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#define MACON3_FRMLNEN 0x02
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#define MACON3_FULDPX 0x01
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// ENC28J60 MICMD Register Bit Definitions
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#define MICMD_MIISCAN 0x02
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#define MICMD_MIIRD 0x01
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// ENC28J60 MISTAT Register Bit Definitions
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#define MISTAT_NVALID 0x04
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#define MISTAT_SCAN 0x02
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#define MISTAT_BUSY 0x01
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// ENC28J60 EBSTCON Register Bit Definitions
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#define EBSTCON_PSV2 0x80
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#define EBSTCON_PSV1 0x40
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#define EBSTCON_PSV0 0x20
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#define EBSTCON_PSEL 0x10
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#define EBSTCON_TMSEL1 0x08
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#define EBSTCON_TMSEL0 0x04
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#define EBSTCON_TME 0x02
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#define EBSTCON_BISTST 0x01
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// PHY registers
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#define PHCON1 0x00
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#define PHSTAT1 0x01
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#define PHHID1 0x02
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#define PHHID2 0x03
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#define PHCON2 0x10
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#define PHSTAT2 0x11
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#define PHIE 0x12
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#define PHIR 0x13
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#define PHLCON 0x14
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// ENC28J60 PHY PHCON1 Register Bit Definitions
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#define PHCON1_PRST 0x8000
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#define PHCON1_PLOOPBK 0x4000
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#define PHCON1_PPWRSV 0x0800
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#define PHCON1_PDPXMD 0x0100
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// ENC28J60 PHY PHSTAT1 Register Bit Definitions
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#define PHSTAT1_PFDPX 0x1000
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#define PHSTAT1_PHDPX 0x0800
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#define PHSTAT1_LLSTAT 0x0004
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#define PHSTAT1_JBSTAT 0x0002
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// ENC28J60 PHY PHCON2 Register Bit Definitions
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#define PHCON2_FRCLINK 0x4000
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#define PHCON2_TXDIS 0x2000
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#define PHCON2_JABBER 0x0400
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#define PHCON2_HDLDIS 0x0100
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// ENC28J60 Packet Control Byte Bit Definitions
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#define PKTCTRL_PHUGEEN 0x08
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#define PKTCTRL_PPADEN 0x04
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#define PKTCTRL_PCRCEN 0x02
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#define PKTCTRL_POVERRIDE 0x01
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// SPI operation codes
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#define ENC28J60_READ_CTRL_REG 0x00
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#define ENC28J60_READ_BUF_MEM 0x3A
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#define ENC28J60_WRITE_CTRL_REG 0x40
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#define ENC28J60_WRITE_BUF_MEM 0x7A
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#define ENC28J60_BIT_FIELD_SET 0x80
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#define ENC28J60_BIT_FIELD_CLR 0xA0
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#define ENC28J60_SOFT_RESET 0xFF
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// max frame length which the controller will accept:
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// (note: maximum ethernet frame length would be 1518)
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#define MAX_FRAMELEN 1500
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#define SPI_SPEED 10000000
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static byte Enc28j60Bank;
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static byte selectPin;
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static uint8_t selectMask;
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volatile static uint8_t *selectPort;
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void ENC28J60::initSPI () {
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pinMode(selectPin, OUTPUT);
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digitalWrite(selectPin, HIGH);
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pinMode(MOSI, OUTPUT);
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pinMode(SCK, OUTPUT);
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pinMode(MISO, INPUT);
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digitalWrite(MOSI, HIGH);
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digitalWrite(MOSI, LOW);
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digitalWrite(SCK, LOW);
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#ifdef ARDUINO_ARCH_AVR
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selectPort = portOutputRegister(digitalPinToPort(selectPin));
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selectMask = digitalPinToBitMask(selectPin);
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#endif
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}
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static void enableChip () {
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#ifdef ARDUINO_ARCH_AVR
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cli();
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*selectPort &= ~selectMask;
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sei();
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#else
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digitalWrite(selectPin, LOW);
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#endif
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}
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static void disableChip () {
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#ifdef ARDUINO_ARCH_AVR
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cli();
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*selectPort |= selectMask;
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sei();
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#else
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digitalWrite(selectPin, HIGH);
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#endif
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}
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static void beginTransaction() {
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SPI.beginTransaction(SPISettings(SPI_SPEED, MSBFIRST, SPI_MODE0));
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enableChip();
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}
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static void endTransaction() {
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disableChip();
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SPI.endTransaction();
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}
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static byte readOp (byte op, byte address) {
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beginTransaction();
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SPI.transfer(op | (address & ADDR_MASK));
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byte result = SPI.transfer(0x00);
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if (address & 0x80)
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result = SPI.transfer(0x00);
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endTransaction();
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return result;
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}
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static void writeOp (byte op, byte address, byte data) {
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beginTransaction();
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SPI.transfer(op | (address & ADDR_MASK));
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SPI.transfer(data);
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endTransaction();
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}
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static void readBuf(uint16_t len, byte* data) {
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beginTransaction();
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SPI.transfer(ENC28J60_READ_BUF_MEM);
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while (len--)
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*data++ = SPI.transfer(0x00);
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endTransaction();
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}
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static void writeBuf(uint16_t len, const byte* data) {
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beginTransaction();
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SPI.transfer(ENC28J60_WRITE_BUF_MEM);
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while (len--)
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SPI.transfer(*data++);
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endTransaction();
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}
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static void SetBank (byte address) {
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if ((address & BANK_MASK) != Enc28j60Bank) {
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writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_BSEL1|ECON1_BSEL0);
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Enc28j60Bank = address & BANK_MASK;
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, Enc28j60Bank>>5);
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}
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}
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static byte readRegByte (byte address) {
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SetBank(address);
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return readOp(ENC28J60_READ_CTRL_REG, address);
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}
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static uint16_t readReg(byte address) {
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return readRegByte(address) + (readRegByte(address+1) << 8);
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}
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static void writeRegByte (byte address, byte data) {
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SetBank(address);
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writeOp(ENC28J60_WRITE_CTRL_REG, address, data);
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}
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static void writeReg(byte address, uint16_t data) {
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writeRegByte(address, data);
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writeRegByte(address + 1, data >> 8);
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}
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static uint16_t readPhyByte (byte address) {
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writeRegByte(MIREGADR, address);
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writeRegByte(MICMD, MICMD_MIIRD);
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while (readRegByte(MISTAT) & MISTAT_BUSY)
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;
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writeRegByte(MICMD, 0x00);
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return readRegByte(MIRD+1);
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}
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static void writePhy (byte address, uint16_t data) {
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writeRegByte(MIREGADR, address);
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writeReg(MIWR, data);
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while (readRegByte(MISTAT) & MISTAT_BUSY)
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;
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}
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byte ENC28J60::initialize (uint16_t size, const byte* macaddr, byte csPin) {
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bufferSize = size;
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selectPin = csPin;
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initSPI();
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disableChip();
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writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
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delay(2); // errata B7/2
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while (!readOp(ENC28J60_READ_CTRL_REG, ESTAT) & ESTAT_CLKRDY)
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;
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writeReg(ERXST, RXSTART_INIT);
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writeReg(ERXRDPT, RXSTART_INIT);
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writeReg(ERXND, RXSTOP_INIT);
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writeReg(ETXST, TXSTART_INIT);
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writeReg(ETXND, TXSTOP_INIT);
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// Stretch pulses for LED, LED_A=Link, LED_B=activity
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writePhy(PHLCON, 0x476);
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writeRegByte(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN|ERXFCON_BCEN);
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writeReg(EPMM0, 0x303f);
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writeReg(EPMCS, 0xf7f9);
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writeRegByte(MACON1, MACON1_MARXEN);
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writeOp(ENC28J60_BIT_FIELD_SET, MACON3,
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MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
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writeReg(MAIPG, 0x0C12);
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writeRegByte(MABBIPG, 0x12);
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writeReg(MAMXFL, MAX_FRAMELEN);
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writeRegByte(MAADR5, macaddr[0]);
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writeRegByte(MAADR4, macaddr[1]);
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writeRegByte(MAADR3, macaddr[2]);
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writeRegByte(MAADR2, macaddr[3]);
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writeRegByte(MAADR1, macaddr[4]);
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writeRegByte(MAADR0, macaddr[5]);
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writePhy(PHCON2, PHCON2_HDLDIS);
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SetBank(ECON1);
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writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
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byte rev = readRegByte(EREVID);
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// microchip forgot to step the number on the silicon when they
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// released the revision B7. 6 is now rev B7. We still have
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// to see what they do when they release B8. At the moment
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// there is no B8 out yet
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if (rev > 5) ++rev;
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return rev;
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}
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bool ENC28J60::isLinkUp() {
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return (readPhyByte(PHSTAT2) >> 2) & 1;
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}
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/*
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struct __attribute__((__packed__)) transmit_status_vector {
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uint16_t transmitByteCount;
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byte transmitCollisionCount : 4;
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byte transmitCrcError : 1;
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byte transmitLengthCheckError : 1;
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byte transmitLengthOutRangeError : 1;
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byte transmitDone : 1;
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byte transmitMulticast : 1;
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byte transmitBroadcast : 1;
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byte transmitPacketDefer : 1;
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byte transmitExcessiveDefer : 1;
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byte transmitExcessiveCollision : 1;
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byte transmitLateCollision : 1;
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byte transmitGiant : 1;
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byte transmitUnderrun : 1;
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uint16_t totalTransmitted;
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byte transmitControlFrame : 1;
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byte transmitPauseControlFrame : 1;
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byte backpressureApplied : 1;
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byte transmitVLAN : 1;
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byte zero : 4;
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};
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*/
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struct transmit_status_vector {
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uint8_t bytes[7];
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};
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#if ETHERCARD_SEND_PIPELINING
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#define BREAKORCONTINUE retry=0; continue;
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#else
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#define BREAKORCONTINUE break;
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#endif
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void ENC28J60::packetSend(uint16_t len) {
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byte retry = 0;
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#if ETHERCARD_SEND_PIPELINING
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goto resume_last_transmission;
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#endif
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while (1) {
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// latest errata sheet: DS80349C
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// always reset transmit logic (Errata Issue 12)
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// the Microchip TCP/IP stack implementation used to first check
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// whether TXERIF is set and only then reset the transmit logic
|
|
// but this has been changed in later versions; possibly they
|
|
// have a reason for this; they don't mention this in the errata
|
|
// sheet
|
|
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
|
|
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
|
|
writeOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXERIF|EIR_TXIF);
|
|
|
|
// prepare new transmission
|
|
if (retry == 0) {
|
|
writeReg(EWRPT, TXSTART_INIT);
|
|
writeReg(ETXND, TXSTART_INIT+len);
|
|
writeOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
|
|
writeBuf(len, buffer);
|
|
}
|
|
|
|
// initiate transmission
|
|
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
|
|
#if ETHERCARD_SEND_PIPELINING
|
|
if (retry == 0) return;
|
|
#endif
|
|
|
|
resume_last_transmission:
|
|
|
|
// wait until transmission has finished; referring to the data sheet and
|
|
// to the errata (Errata Issue 13; Example 1) you only need to wait until either
|
|
// TXIF or TXERIF gets set; however this leads to hangs; apparently Microchip
|
|
// realized this and in later implementations of their tcp/ip stack they introduced
|
|
// a counter to avoid hangs; of course they didn't update the errata sheet
|
|
uint16_t count = 0;
|
|
while ((readRegByte(EIR) & (EIR_TXIF | EIR_TXERIF)) == 0 && ++count < 1000U)
|
|
;
|
|
|
|
if (!(readRegByte(EIR) & EIR_TXERIF) && count < 1000U) {
|
|
// no error; start new transmission
|
|
BREAKORCONTINUE
|
|
}
|
|
|
|
// cancel previous transmission if stuck
|
|
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
|
|
|
|
#if ETHERCARD_RETRY_LATECOLLISIONS == 0
|
|
BREAKORCONTINUE
|
|
#endif
|
|
|
|
// Check whether the chip thinks that a late collision occurred; the chip
|
|
// may be wrong (Errata Issue 13); therefore we retry. We could check
|
|
// LATECOL in the ESTAT register in order to find out whether the chip
|
|
// thinks a late collision occurred but (Errata Issue 15) tells us that
|
|
// this is not working. Therefore we check TSV
|
|
transmit_status_vector tsv;
|
|
uint16_t etxnd = readReg(ETXND);
|
|
writeReg(ERDPT, etxnd+1);
|
|
readBuf(sizeof(transmit_status_vector), (byte*) &tsv);
|
|
// LATECOL is bit number 29 in TSV (starting from 0)
|
|
|
|
if (!((readRegByte(EIR) & EIR_TXERIF) && (tsv.bytes[3] & 1<<5) /*tsv.transmitLateCollision*/) || retry > 16U) {
|
|
// there was some error but no LATECOL so we do not repeat
|
|
BREAKORCONTINUE
|
|
}
|
|
|
|
retry++;
|
|
}
|
|
}
|
|
|
|
|
|
uint16_t ENC28J60::packetReceive() {
|
|
static uint16_t gNextPacketPtr = RXSTART_INIT;
|
|
static bool unreleasedPacket = false;
|
|
uint16_t len = 0;
|
|
|
|
if (unreleasedPacket) {
|
|
if (gNextPacketPtr == 0)
|
|
writeReg(ERXRDPT, RXSTOP_INIT);
|
|
else
|
|
writeReg(ERXRDPT, gNextPacketPtr - 1);
|
|
unreleasedPacket = false;
|
|
}
|
|
|
|
if (readRegByte(EPKTCNT) > 0) {
|
|
writeReg(ERDPT, gNextPacketPtr);
|
|
|
|
struct {
|
|
uint16_t nextPacket;
|
|
uint16_t byteCount;
|
|
uint16_t status;
|
|
} header;
|
|
|
|
readBuf(sizeof header, (byte*) &header);
|
|
|
|
gNextPacketPtr = header.nextPacket;
|
|
len = header.byteCount - 4; //remove the CRC count
|
|
if (len>bufferSize) len=0; // discard messages too long **NMCK**
|
|
if ((header.status & 0x80)==0)
|
|
len = 0;
|
|
else
|
|
readBuf(len, buffer);
|
|
unreleasedPacket = true;
|
|
|
|
writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
|
|
}
|
|
return len;
|
|
}
|
|
|
|
// Contributed by Alex M. Based on code from: http://blog.derouineau.fr
|
|
// /2011/07/putting-enc28j60-ethernet-controler-in-sleep-mode/
|
|
void ENC28J60::powerDown() {
|
|
writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
|
|
while(readRegByte(ESTAT) & ESTAT_RXBUSY);
|
|
while(readRegByte(ECON1) & ECON1_TXRTS);
|
|
writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_VRPS);
|
|
writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PWRSV);
|
|
}
|
|
|
|
void ENC28J60::powerUp() {
|
|
writeOp(ENC28J60_BIT_FIELD_CLR, ECON2, ECON2_PWRSV);
|
|
while(!readRegByte(ESTAT) & ESTAT_CLKRDY);
|
|
writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
|
|
}
|
|
|
|
void ENC28J60::enableBroadcast (bool temporary) {
|
|
writeRegByte(ERXFCON, readRegByte(ERXFCON) | ERXFCON_BCEN);
|
|
if(!temporary)
|
|
broadcast_enabled = true;
|
|
}
|
|
|
|
void ENC28J60::disableBroadcast (bool temporary) {
|
|
if(!temporary)
|
|
broadcast_enabled = false;
|
|
if(!broadcast_enabled)
|
|
writeRegByte(ERXFCON, readRegByte(ERXFCON) & ~ERXFCON_BCEN);
|
|
}
|
|
|
|
void ENC28J60::enableMulticast () {
|
|
writeRegByte(ERXFCON, readRegByte(ERXFCON) | ERXFCON_MCEN);
|
|
}
|
|
|
|
void ENC28J60::disableMulticast () {
|
|
writeRegByte(ERXFCON, readRegByte(ERXFCON) & ~ERXFCON_MCEN);
|
|
}
|
|
|
|
void ENC28J60::enablePromiscuous (bool temporary) {
|
|
writeRegByte(ERXFCON, readRegByte(ERXFCON) & ERXFCON_CRCEN);
|
|
if(!temporary)
|
|
promiscuous_enabled = true;
|
|
}
|
|
|
|
void ENC28J60::disablePromiscuous (bool temporary) {
|
|
if(!temporary)
|
|
promiscuous_enabled = false;
|
|
if(!promiscuous_enabled) {
|
|
writeRegByte(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN|ERXFCON_BCEN);
|
|
}
|
|
}
|