diff --git a/ram/ram/apps.py b/ram/ram/apps.py
new file mode 100644
index 0000000..b9aa00a
--- /dev/null
+++ b/ram/ram/apps.py
@@ -0,0 +1,14 @@
+from django.conf import settings
+from django.apps import AppConfig
+
+
+class RamConfig(AppConfig):
+    name = "ram"
+
+    def ready(self):
+        cache_middleware = set([
+            "django.middleware.cache.UpdateCacheMiddleware",
+            "django.middleware.cache.FetchFromCacheMiddleware",
+        ])
+        if cache_middleware.issubset(settings.MIDDLEWARE):
+            from ram.signals import clear_cache  # noqa: F401
diff --git a/ram/ram/signals.py b/ram/ram/signals.py
new file mode 100644
index 0000000..34b7c9d
--- /dev/null
+++ b/ram/ram/signals.py
@@ -0,0 +1,8 @@
+from django.core.cache import cache
+from django.db.models.signals import post_save
+from django.dispatch import receiver
+
+
+@receiver(post_save)
+def clear_cache(sender, **kwargs):
+    cache.clear()
diff --git a/ram/roster/admin.py b/ram/roster/admin.py
index 5f3b781..d419b8f 100644
--- a/ram/roster/admin.py
+++ b/ram/roster/admin.py
@@ -28,6 +28,7 @@ class RollingClass(admin.ModelAdmin):
         "company__name",
         "type__type",
     )
+    save_as = True
 
 
 class RollingStockDocInline(admin.TabularInline):