mirror of
https://github.com/DCC-EX/CommandStation-EX.git
synced 2024-11-23 08:06:13 +01:00
Initial I2C native driver
This commit is contained in:
pmantoine
parent
94d0aa92d9
commit
83325ebf78
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@ -38,7 +38,10 @@
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* bus on the SAMD architecture
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***************************************************************************/
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#if defined(I2C_USE_INTERRUPTS) && defined(ARDUINO_ARCH_STM32)
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void I2C1_IRQHandler() {
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extern "C" void I2C1_EV_IRQHandler(void) {
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I2CManager.handleInterrupt();
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}
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extern "C" void I2C1_ER_IRQHandler(void) {
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I2CManager.handleInterrupt();
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}
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#endif
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@ -91,44 +94,60 @@ void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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// Use 10x the rise time spec to enable integer divide of 62.5ns clock period
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uint16_t t_rise;
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uint32_t ccr_freq;
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if (i2cClockSpeed < 200000L) {
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// i2cClockSpeed = 100000L;
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t_rise = 0x11; // (1000ns /62.5ns) + 1;
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}
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else if (i2cClockSpeed < 800000L)
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while (s->CR1 & I2C_CR1_STOP); // Prevents lockup by guarding further
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// writes to CR1 while STOP is being executed!
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// Disable the I2C device, as TRISE can only be programmed whilst disabled
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s->CR1 &= ~(I2C_CR1_PE); // Disable I2C
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// Software reset the I2C peripheral
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// s->CR1 |= I2C_CR1_SWRST; // reset the I2C
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// delay(1);
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// Release reset
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// s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
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if (i2cClockSpeed > 100000L)
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{
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i2cClockSpeed = 400000L;
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t_rise = 0x06; // (300ns / 62.5ns) + 1;
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// } else if (i2cClockSpeed < 1200000L) {
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// i2cClockSpeed = 1000000L;
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// t_rise = 120;
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if (i2cClockSpeed > 400000L)
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i2cClockSpeed = 400000L;
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t_rise = 0x06; // (300ns /62.5ns) + 1;
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}
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else
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{
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i2cClockSpeed = 100000L;
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t_rise = 0x11; // (1000ns /62.5ns) + 1;
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}
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// Configure the rise time register
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s->TRISE = t_rise;
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// Enable the I2C master mode
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s->CR1 &= ~(I2C_CR1_PE); // Enable I2C
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// Software reset the I2C peripheral
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// s->CR1 |= I2C_CR1_SWRST; // reset the I2C
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// Release reset
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// s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
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// Calculate baudrate - using a rise time appropriate for the speed
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// DIAG(F("Setting I2C clock to: %d"), i2cClockSpeed);
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// Calculate baudrate
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ccr_freq = I2C_BUSFREQ * 1000000 / i2cClockSpeed / 2;
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// Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
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// Bit 14: Duty, fast mode duty cycle
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// Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns, so CCR divisor must be 0x50 (80 * 62.5ns = 5000ns)
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s->CCR = (uint16_t)ccr_freq;
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// Configure the rise time register
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s->TRISE = t_rise; // 1000 ns / 62.5 ns = 16 + 1
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if (i2cClockSpeed > 100000L)
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s->CCR = (uint16_t)ccr_freq | 0x8000; // We need Fast Mode set
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else
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s->CCR = (uint16_t)ccr_freq;
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// Enable the I2C master mode
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s->CR1 |= I2C_CR1_PE; // Enable I2C
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// Wait for bus to be clear?
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unsigned long startTime = micros();
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bool timeout = false;
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while (s->SR2 & I2C_SR2_BUSY) {
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if (micros() - startTime >= 500UL) {
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timeout = true;
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break;
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}
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}
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if (timeout) {
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digitalWrite(D13, HIGH);
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DIAG(F("I2C: SR2->BUSY timeout"));
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// delay(1000);
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}
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}
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/***************************************************************************
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@ -136,32 +155,46 @@ void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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***************************************************************************/
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void I2CManagerClass::I2C_init()
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{
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//Setting up the clocks
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RCC->APB1ENR |= (1<<21); // Enable I2C CLOCK
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RCC->AHB1ENR |= (1<<1); // Enable GPIOB CLOCK for PB8/PB9
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// Setting up the clocks
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;//(1 << 21); // Enable I2C CLOCK
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// Reset the I2C1 peripheral to initial state
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RCC->APB1RSTR |= RCC_APB1RSTR_I2C1RST;
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RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C1RST;
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// Standard I2C pins are SCL on PB8 and SDA on PB9
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RCC->AHB1ENR |= (1<<1); // Enable GPIOB CLOCK for PB8/PB9
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// Bits (17:16)= 1:0 --> Alternate Function for Pin PB8;
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// Bits (19:18)= 1:0 --> Alternate Function for Pin PB9
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GPIOB->MODER &= ~((3<<(8*2)) | (3<<(9*2))); // Clear all MODER bits for PB8 and PB9
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GPIOB->MODER |= (2<<(8*2)) | (2<<(9*2)); // PB8 and PB9 set to ALT function
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GPIOB->OTYPER |= (1<<8) | (1<<9); // PB8 and PB9 set to open drain output capability
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GPIOB->OSPEEDR |= (3<<(8*2)) | (3<<(9*2)); // PB8 and PB9 set to High Speed mode
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GPIOB->PUPDR &= ~((3<<(8*2)) | (3<<(9*2))); // Clear all PUPDR bits for PB8 and PB9
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GPIOB->PUPDR |= (1<<(8*2)) | (1<<(9*2)); // PB8 and PB9 set to pull-up capability
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// Alt Function High register routing pins PB8 and PB9 for I2C1:
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// Bits (3:2:1:0) = 0:1:0:0 --> AF4 for pin PB8
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// Bits (7:6:5:4) = 0:1:0:0 --> AF4 for pin PB9
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GPIOB->AFR[1] &= ~((15<<0) | (15<<4)); // Clear all AFR bits for PB8 on low nibble, PB9 on next nibble up
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GPIOB->AFR[1] |= (4<<0) | (4<<4); // PB8 on low nibble, PB9 on next nibble up
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// Software reset the I2C peripheral
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// // Software reset the I2C peripheral
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s->CR1 |= I2C_CR1_SWRST; // reset the I2C
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s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
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asm("nop"); // wait a bit... suggestion from online!
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s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
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// Clear all bits in I2C CR2 register except reserved bits
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s->CR2 &= 0xE000;
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// Program the peripheral input clock in CR2 Register in order to generate correct timings
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s->CR2 |= I2C_BUSFREQ; // PCLK1 FREQUENCY in MHz
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// set own address to 00 - not really used in master mode
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I2C1->OAR1 |= (1 << 14); // bit 14 should be kept at 1 according to the datasheet
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#if defined(I2C_USE_INTERRUPTS)
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// Setting NVIC
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NVIC_SetPriority(I2C_IRQn, 1); // Match default priorities
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NVIC_EnableIRQ(I2C_IRQn);
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NVIC_SetPriority(I2C1_EV_IRQn, 1); // Match default priorities
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NVIC_EnableIRQ(I2C1_EV_IRQn);
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NVIC_SetPriority(I2C1_ER_IRQn, 1); // Match default priorities
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NVIC_EnableIRQ(I2C1_ER_IRQn);
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// CR2 Interrupt Settings
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// Bit 15-13: reserved
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@ -172,8 +205,8 @@ void I2CManagerClass::I2C_init()
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// Bit 8: ITERREN - Error interrupt enable
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// Bit 7-6: reserved
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// Bit 5-0: FREQ - Peripheral clock frequency (max 50MHz)
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// s->CR2 |= 0x0700; // Enable Buffer, Event and Error interrupts
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s->CR2 |= 0x0300; // Enable Event and Error interrupts
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s->CR2 |= 0x0700; // Enable Buffer, Event and Error interrupts
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// s->CR2 |= 0x0300; // Enable Event and Error interrupts
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#endif
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// Calculate baudrate and set default rate for now
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@ -181,14 +214,26 @@ void I2CManagerClass::I2C_init()
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// Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
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// Bit 14: Duty, fast mode duty cycle
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// Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns, so CCR divisor must be 0x50 (80 * 62.5ns = 5000ns)
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s->CCR = 0x0050;
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s->CCR = 0x50;
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// Configure the rise time register - max allowed in 1000ns
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s->TRISE = 0x0011; // 1000 ns / 62.5 ns = 16 + 1
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// Enable the I2C master mode
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s->CR1 |= I2C_CR1_PE; // Enable I2C
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// Setting bus idle mode and wait for sync
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// Wait for bus to be clear?
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unsigned long startTime = micros();
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bool timeout = false;
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while (s->SR2 & I2C_SR2_BUSY) {
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if (micros() - startTime >= 500UL) {
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timeout = true;
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break;
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}
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}
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if (timeout) {
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DIAG(F("I2C: SR2->BUSY timeout"));
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// delay(1000);
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}
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}
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/***************************************************************************
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@ -198,49 +243,56 @@ void I2CManagerClass::I2C_sendStart() {
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// Set counters here in case this is a retry.
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rxCount = txCount = 0;
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uint8_t temp;
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// On a single-master I2C bus, the start bit won't be sent until the bus
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// state goes to IDLE so we can request it without waiting. On a
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// multi-master bus, the bus may be BUSY under control of another master,
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// On a single-master I2C bus, the start bit won't be sent until the bus
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// state goes to IDLE so we can request it without waiting. On a
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// multi-master bus, the bus may be BUSY under control of another master,
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// in which case we can avoid some arbitration failures by waiting until
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// the bus state is IDLE. We don't do that here.
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// If anything to send, initiate write. Otherwise initiate read.
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if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
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{
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// Send start for read operation
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s->CR1 |= I2C_CR1_ACK; // Enable the ACK
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s->CR1 |= I2C_CR1_START; // Generate START
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// Send address with read flag (1) or'd in
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s->DR = (deviceAddress << 1) | 1; // send the address
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while (!(s->SR1 && I2C_SR1_ADDR)); // wait for ADDR bit to set
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// Special case for 1 byte reads!
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if (bytesToReceive == 1)
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{
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s->CR1 &= ~I2C_CR1_ACK; // clear the ACK bit
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temp = I2C1->SR1 | I2C1->SR2; // read SR1 and SR2 to clear the ADDR bit.... EV6 condition
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s->CR1 |= I2C_CR1_STOP; // Stop I2C
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// Send start for read operation
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while (s->CR1 & I2C_CR1_STOP); // Prevents lockup by guarding further
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// writes to CR1 while STOP is being executed!
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// Wait for bus to be clear?
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unsigned long startTime = micros();
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bool timeout = false;
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while (s->SR2 & I2C_SR2_BUSY) {
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if (micros() - startTime >= 500UL) {
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timeout = true;
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break;
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}
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else
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temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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else {
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// Send start for write operation
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s->CR1 |= I2C_CR1_ACK; // Enable the ACK
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s->CR1 |= I2C_CR1_START; // Generate START
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// Send address with write flag (0) or'd in
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s->DR = (deviceAddress << 1) | 0; // send the address
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while (!(s->SR1 && I2C_SR1_ADDR)); // wait for ADDR bit to set
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temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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if (timeout) {
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DIAG(F("I2C_sendStart: SR2->BUSY timeout"));
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// delay(1000);
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}
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s->CR1 |= I2C_CR1_ACK; // Enable the ACK
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s->CR1 &= ~(I2C_CR1_POS); // Reset the POS bit - only used for 2-byte reception
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s->CR1 |= I2C_CR1_START; // Generate START
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}
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/***************************************************************************
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* Initiate a stop bit for transmission (does not interrupt)
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***************************************************************************/
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void I2CManagerClass::I2C_sendStop() {
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s->CR1 |= I2C_CR1_STOP; // Stop I2C
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uint32_t temp;
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s->CR1 |= I2C_CR1_STOP; // Stop I2C
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temp = s->SR1 | s->SR2; // Read the status registers to clear them
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while (s->CR1 & I2C_CR1_STOP); // Prevents lockup by guarding further
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// writes to CR1 while STOP is being executed!
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// Wait for bus to be clear?
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unsigned long startTime = micros();
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bool timeout = false;
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while (s->SR2 & I2C_SR2_BUSY) {
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if (micros() - startTime >= 500UL) {
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timeout = true;
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break;
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}
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}
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if (timeout) {
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DIAG(F("I2C_sendStop: SR2->BUSY timeout"));
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// delay(1000);
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}
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}
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/***************************************************************************
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@ -252,9 +304,11 @@ void I2CManagerClass::I2C_close() {
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s->CR1 &= ~I2C_CR1_PE; // Disable I2C peripheral
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// Should never happen, but wait for up to 500us only.
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unsigned long startTime = micros();
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while ((s->CR1 && I2C_CR1_PE) != 0) {
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while ((s->CR1 & I2C_CR1_PE) != 0) {
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if (micros() - startTime >= 500UL) break;
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}
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NVIC_DisableIRQ(I2C1_EV_IRQn);
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NVIC_DisableIRQ(I2C1_ER_IRQn);
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}
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/***************************************************************************
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@ -263,50 +317,158 @@ void I2CManagerClass::I2C_close() {
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* (and therefore, indirectly, from I2CRB::wait() and I2CRB::isBusy()).
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***************************************************************************/
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void I2CManagerClass::I2C_handleInterrupt() {
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volatile uint16_t temp_sr1, temp_sr2, temp;
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static bool led_lit = false;
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if (s->SR1 && I2C_SR1_ARLO) {
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temp_sr1 = s->SR1;
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// if (temp_sr1 & I2C_SR1_ADDR)
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// temp_sr2 = s->SR2;
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// Check to see if start bit sent - SB interrupt!
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if (temp_sr1 & I2C_SR1_SB)
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{
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// If anything to send, initiate write. Otherwise initiate read.
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if (operation == OPERATION_READ || ((operation == OPERATION_REQUEST) && !bytesToSend))
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{
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// Send address with read flag (1) or'd in
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s->DR = (deviceAddress << 1) | 1; // send the address
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// while (!(s->SR1 & I2C_SR1_ADDR)); // wait for ADDR bit to set
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// // // Special case for 1 byte reads!
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// if (bytesToReceive == 1)
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// {
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// s->CR1 &= ~I2C_CR1_ACK; // clear the ACK bit
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// temp = I2C1->SR1 | I2C1->SR2; // read SR1 and SR2 to clear the ADDR bit.... EV6 condition
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// s->CR1 |= I2C_CR1_STOP; // Stop I2C
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// }
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// else
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// temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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else
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{
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// Send address with write flag (0) or'd in
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s->DR = (deviceAddress << 1) | 0; // send the address
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// while (!(s->SR1 & I2C_SR1_ADDR)); // wait for ADDR bit to set
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// temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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// while (!(s->SR1 & I2C_SR1_ADDR)); // wait for ADDR bit to set
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// temp = s->SR1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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else if (temp_sr1 & I2C_SR1_ADDR) {
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// Receive 1 byte (AN2824 figure 2)
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if (bytesToReceive == 1) {
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s->CR1 &= ~I2C_CR1_ACK; // Disable ACK final byte
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// EV6_1 must be atomic operation (AN2824)
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// noInterrupts();
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(void)s->SR2; // read SR2 to complete clearing the ADDR bit
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I2C_sendStop(); // send stop
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// interrupts();
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}
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// Receive 2 bytes (AN2824 figure 2)
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else if (bytesToReceive == 2) {
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s->CR1 |= I2C_CR1_POS; // Set POS flag (NACK position next)
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// EV6_1 must be atomic operation (AN2824)
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// noInterrupts();
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(void)s->SR2; // read SR2 to complete clearing the ADDR bit
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s->CR1 &= ~I2C_CR1_ACK; // Disable ACK byte
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// interrupts();
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}
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else
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temp = temp_sr1 | s->SR2; // read SR1 and SR2 to clear the ADDR bit
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}
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else if (temp_sr1 & I2C_SR1_AF)
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{
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s->SR1 &= ~(I2C_SR1_AF); // Clear AF
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s->CR1 &= ~(I2C_CR1_ACK); // Clear ACK
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while (s->SR1 & I2C_SR1_AF); // Check AF cleared
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I2C_sendStop(); // Clear the bus
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completionStatus = I2C_STATUS_NEGATIVE_ACKNOWLEDGE;
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state = I2C_STATE_COMPLETED;
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}
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else if (temp_sr1 & I2C_SR1_ARLO)
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{
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// Arbitration lost, restart
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I2C_sendStart(); // Reinitiate request
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} else if (s->SR1 && I2C_SR1_BERR) {
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s->SR1 &= ~(I2C_SR1_ARLO); // Clear ARLO
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s->CR1 &= ~(I2C_CR1_ACK); // Clear ACK
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I2C_sendStop();
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I2C_sendStart(); // Reinitiate request
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// state = I2C_STATE_COMPLETED;
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}
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else if (temp_sr1 & I2C_SR1_BERR)
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{
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// Bus error
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s->SR1 &= ~(I2C_SR1_BERR); // Clear BERR
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s->CR1 &= ~(I2C_CR1_ACK); // Clear ACK
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I2C_sendStop(); // Clear the bus
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completionStatus = I2C_STATUS_BUS_ERROR;
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state = I2C_STATE_COMPLETED;
|
||||
} else if (s->SR1 && I2C_SR1_TXE) {
|
||||
}
|
||||
else if (temp_sr1 & I2C_SR1_TXE)
|
||||
{
|
||||
// temp_sr2 = s->SR2;
|
||||
// Master write completed
|
||||
if (s->SR1 && (1<<10)) {
|
||||
// Nacked, send stop.
|
||||
if (temp_sr1 & I2C_SR1_AF) {
|
||||
// Nacked
|
||||
s->SR1 &= ~(I2C_SR1_AF); // Clear AF
|
||||
s->CR1 &= ~(I2C_CR1_ACK); // Clear ACK
|
||||
// send stop.
|
||||
I2C_sendStop();
|
||||
completionStatus = I2C_STATUS_NEGATIVE_ACKNOWLEDGE;
|
||||
state = I2C_STATE_COMPLETED;
|
||||
} else if (bytesToSend) {
|
||||
// Acked, so send next byte
|
||||
while ((s->SR1 & I2C_SR1_BTF)); // Check BTF before proceeding
|
||||
s->DR = sendBuffer[txCount++];
|
||||
bytesToSend--;
|
||||
} else if (bytesToReceive) {
|
||||
// Last sent byte acked and no more to send. Send repeated start, address and read bit.
|
||||
// } else if (bytesToReceive) {
|
||||
// // Last sent byte acked and no more to send. Send repeated start, address and read bit.
|
||||
// s->CR1 &= ~(I2C_CR1_ACK); // Clear ACK
|
||||
// I2C_sendStart();
|
||||
// s->I2CM.ADDR.bit.ADDR = (deviceAddress << 1) | 1;
|
||||
} else {
|
||||
// No bytes left to send or receive
|
||||
// Check both TxE/BTF == 1 before generating stop
|
||||
while (!(s->SR1 && I2C_SR1_TXE)); // Check TxE
|
||||
while (!(s->SR1 && I2C_SR1_BTF)); // Check BTF
|
||||
// while (!(s->SR1 & I2C_SR1_TXE)); // Check TxE
|
||||
while ((s->SR1 & I2C_SR1_BTF)); // Check BTF
|
||||
// No more data to send/receive. Initiate a STOP condition and finish
|
||||
s->CR1 &= ~(I2C_CR1_ACK); // Clear ACK
|
||||
I2C_sendStop();
|
||||
// completionStatus = I2C_STATUS_OK;
|
||||
state = I2C_STATE_COMPLETED;
|
||||
}
|
||||
} else if (s->SR1 && I2C_SR1_RXNE) {
|
||||
}
|
||||
else if (temp_sr1 & I2C_SR1_RXNE)
|
||||
{
|
||||
// Master read completed without errors
|
||||
if (bytesToReceive == 1) {
|
||||
// s->I2CM.CTRLB.bit.ACKACT = 1; // NAK final byte
|
||||
s->CR1 &= ~I2C_CR1_ACK; // NAK final byte
|
||||
I2C_sendStop(); // send stop
|
||||
receiveBuffer[rxCount++] = s->DR; // Store received byte
|
||||
bytesToReceive = 0;
|
||||
// completionStatus = I2C_STATUS_OK;
|
||||
state = I2C_STATE_COMPLETED;
|
||||
} else if (bytesToReceive) {
|
||||
// s->I2CM.CTRLB.bit.ACKACT = 0; // ACK all but final byte
|
||||
}
|
||||
else if (bytesToReceive == 2)
|
||||
{
|
||||
// Also needs to be atomic!
|
||||
// noInterrupts();
|
||||
I2C_sendStop();
|
||||
receiveBuffer[rxCount++] = s->DR; // Store received byte
|
||||
// interrupts();
|
||||
}
|
||||
else if (bytesToReceive)
|
||||
{
|
||||
s->CR1 &= ~(I2C_CR1_ACK); // ACK all but final byte
|
||||
receiveBuffer[rxCount++] = s->DR; // Store received byte
|
||||
bytesToReceive--;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// DIAG(F("Unhandled I2C interrupt!"));
|
||||
led_lit = ~led_lit;
|
||||
digitalWrite(D13, led_lit);
|
||||
// delay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* I2CMANAGER_STM32_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user