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I2cRailcom
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Asbelos
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252
IO_I2CRailcom.h
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252
IO_I2CRailcom.h
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/*
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* © 2024, Chris Harlow. All rights reserved.
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* © 2023, Neil McKechnie. All rights reserved.
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*
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* This file is part of DCC++EX API
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*
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* This is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* It is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with CommandStation. If not, see <https://www.gnu.org/licenses/>.
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*/
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/*
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*
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* Dec 2023, Added NXP SC16IS752 I2C Dual UART
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* The SC16IS752 has 64 bytes TX & RX FIFO buffer
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* First version without interrupts from I2C UART and only RX/TX are used, interrupts may not be
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* needed as the RX Fifo holds the reply
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*
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* Jan 2024, Issue with using both UARTs simultaniously, the secod uart seems to work but the first transmit
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* corrupt data. This need more analysis and experimenatation.
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* Will push this driver to the dev branch with the uart fixed to 0
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* Both SC16IS750 (single uart) and SC16IS752 (dual uart, but only uart 0 is enable)
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*
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* myHall.cpp configuration syntax:
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*
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* I2CRailcom::create(1st vPin, vPins, I2C address, xtal);
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*
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* Parameters:
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* 1st vPin : First virtual pin that EX-Rail can control to play a sound, use PLAYSOUND command (alias of ANOUT)
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* vPins : Total number of virtual pins allocated (2 vPins are supported, one for each UART)
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* 1st vPin for UART 0, 2nd for UART 1
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* I2C Address : I2C address of the serial controller, in 0x format
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*/
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#ifndef IO_I2CRailcom_h
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#define IO_I2CRailcom_h
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#include "IODevice.h"
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#include "I2CManager.h"
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#include "DIAG.h"
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// Debug and diagnostic defines, enable too many will result in slowing the driver
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#define DIAG_I2CRailcom
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#define DIAG_I2CRailcom_data
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#define DIAG_I2CRailcom_reg
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class I2CRailcom : public IODevice {
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private:
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// SC16IS752 defines
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uint8_t _UART_CH=0x00;
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// Communication parameters for the DFPlayer are fixed at 8 bit, No parity, 1 stopbit
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const uint8_t WORD_LEN = 0x03; // Value LCR bit 0,1
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const uint8_t STOP_BIT = 0x00; // Value LCR bit 2
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const uint8_t PARITY_ENA = 0x00; // Value LCR bit 3
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const uint8_t PARITY_TYPE = 0x00; // Value LCR bit 4
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const uint32_t BAUD_RATE = 9600;
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const uint8_t PRESCALER = 0x01; // Value MCR bit 7
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const unsigned long SC16IS752_XTAL_FREQ_RAILCOM = 16000000; // Baud rate for Railcom signal
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byte _inbuf[65];
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byte _outbuf[2];
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public:
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// Constructor
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I2CRailcom(VPIN firstVpin, int nPins, I2CAddress i2cAddress){
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_firstVpin = firstVpin;
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_nPins = nPins;
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_I2CAddress = i2cAddress;
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addDevice(this);
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}
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public:
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static void create(VPIN firstVpin, int nPins, I2CAddress i2cAddress) {
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if (nPins>2) nPins=2;
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if (checkNoOverlap(firstVpin, nPins, i2cAddress))
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new I2CRailcom(firstVpin, nPins, i2cAddress);
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}
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void _begin() override {
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I2CManager.setClock(1000000); // TODO do we need this?
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I2CManager.begin();
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auto exists=I2CManager.exists(_I2CAddress);
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DIAG(F("I2CRailcom: %s UART%S detected"),
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_I2CAddress.toString(), exists?F(""):F(" NOT"));
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if (!exists) return;
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_UART_CH=0;
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Init_SC16IS752(); // Initialize UART0
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if (_nPins>1) {
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_UART_CH=1;
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Init_SC16IS752(); // Initialize UART1
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}
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if (_deviceState==DEVSTATE_INITIALISING) _deviceState=DEVSTATE_NORMAL;
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_display();
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}
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void _loop(unsigned long currentMicros) override {
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// Read responses from device
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if (_deviceState!=DEVSTATE_NORMAL) return;
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// TODO - return if in cutout or cutout very soon.
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// flip channels each loop
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if (_nPins>1) _UART_CH=_UART_CH?0:1;
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// Read incoming raw Railcom data, and process accordingly
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auto inlength= UART_ReadRegister(REG_RXLV);
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if (inlength==0) return;
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{
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#ifdef DIAG_I2CRailcom
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DIAG(F("Railcom: %s/%d RX Fifo: %d"),_I2CAddress.toString(), _UART_CH, inlength);
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#endif
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_outbuf[0]=(byte)(REG_RHR << 3 | _UART_CH << 1);
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I2CManager.read(_I2CAddress, _inbuf, inlength, _outbuf, 1);
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#ifdef DIAG_I2CRailcom_data
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DIAG(F("Railcom %s/%d RX FIFO Data"), _I2CAddress.toString(), _UART_CH);
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for (int i = 0; i < inlength; i++){
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DIAG(F("[0x%x]: 0x%x"), i, _inbuf[i]);
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}
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#endif
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}
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}
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void _display() override {
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DIAG(F("I2CRailcom Configured on Vpins:%u-%u %S"), _firstVpin, _firstVpin+_nPins-1,
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(_deviceState!=DEVSTATE_NORMAL) ? F("OFFLINE") : F(""));
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}
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private:
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// SC16IS752 functions
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// Initialise SC16IS752 only for this channel
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// First a software reset
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// Enable FIFO and clear TX & RX FIFO
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// Need to set the following registers
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// IOCONTROL set bit 1 and 2 to 0 indicating that they are GPIO
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// IODIR set all bit to 1 indicating al are output
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// IOSTATE set only bit 0 to 1 for UART 0, or only bit 1 for UART 1 //
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// LCR bit 7=0 divisor latch (clock division registers DLH & DLL, they store 16 bit divisor),
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// WORD_LEN, STOP_BIT, PARITY_ENA and PARITY_TYPE
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// MCR bit 7=0 clock divisor devide-by-1 clock input
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// DLH most significant part of divisor
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// DLL least significant part of divisor
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//
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// BAUD_RATE, WORD_LEN, STOP_BIT, PARITY_ENA and PARITY_TYPE have been defined and initialized
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//
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void Init_SC16IS752(){
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//uint16_t _divisor = (SC16IS752_XTAL_FREQ / PRESCALER) / (BAUD_RATE * 16);
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const uint16_t _divisor = (SC16IS752_XTAL_FREQ_RAILCOM / PRESCALER) / (BAUD_RATE * 16); // Calculate _divisor for baudrate
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if (_UART_CH==0) {
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// only reset on channel 0}
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UART_WriteRegister(REG_IOCONTROL, 0x08,false); // UART Software reset
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_deviceState=DEVSTATE_INITIALISING; // ignores error during reset which seems normal.
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}
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UART_WriteRegister(REG_FCR, 0x07,false); // Reset FIFO, clear RX & TX FIFO (write only)
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UART_WriteRegister(REG_MCR, 0x00); // Set MCR to all 0, includes Clock divisor
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UART_WriteRegister(REG_LCR, 0x80 | WORD_LEN | STOP_BIT | PARITY_ENA | PARITY_TYPE); // Divisor latch enabled
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UART_WriteRegister(REG_DLL, _divisor); // Write DLL
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UART_WriteRegister(REG_DLH, (uint8_t)(_divisor >> 8)); // Write DLH
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UART_WriteRegister(REG_LCR, UART_ReadRegister(REG_LCR) & 0x7F); // Divisor latch disabled
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if (_deviceState==DEVSTATE_INITIALISING) {
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DIAG(F("UART %d init complete"),_UART_CH);
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}
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}
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void UART_WriteRegister(uint8_t reg, uint8_t val, bool readback=true){
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_outbuf[0] = (byte)( reg << 3 | _UART_CH << 1);
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_outbuf[1]=val;
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auto status=I2CManager.write(_I2CAddress, _outbuf, (uint8_t)2);
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if(status!=I2C_STATUS_OK) {
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DIAG(F("I2CRailcom %s/%d write reg=0x%x,data=0x%x,I2Cstate=%d"),
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_I2CAddress.toString(), _UART_CH, reg, val, status);
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_deviceState=DEVSTATE_FAILED;
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}
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if (readback) { // Read it back to cross check
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auto readback=UART_ReadRegister(reg);
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if (readback!=val) {
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DIAG(F("I2CRailcom %s/%d reg:0x%x write=0x%x read=0x%x"),_I2CAddress.toString(),_UART_CH,reg,val,readback);
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}
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}
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}
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uint8_t UART_ReadRegister(uint8_t reg){
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_outbuf[0] = (byte)(reg << 3 | _UART_CH << 1); // _outbuffer[0] has now UART_REG and UART_CH
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_inbuf[0]=0;
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auto status=I2CManager.read(_I2CAddress, _inbuf, 1, _outbuf, 1);
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if (status!=I2C_STATUS_OK) {
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DIAG(F("I2CRailcom %s/%d read reg=0x%x,I2Cstate=%d"),
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_I2CAddress.toString(), _UART_CH, reg, status);
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_deviceState=DEVSTATE_FAILED;
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}
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return _inbuf[0];
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}
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// SC16IS752 General register set (from the datasheet)
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enum : uint8_t {
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REG_RHR = 0x00, // FIFO Read
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REG_THR = 0x00, // FIFO Write
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REG_IER = 0x01, // Interrupt Enable Register R/W
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REG_FCR = 0x02, // FIFO Control Register Write
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REG_IIR = 0x02, // Interrupt Identification Register Read
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REG_LCR = 0x03, // Line Control Register R/W
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REG_MCR = 0x04, // Modem Control Register R/W
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REG_LSR = 0x05, // Line Status Register Read
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REG_MSR = 0x06, // Modem Status Register Read
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REG_SPR = 0x07, // Scratchpad Register R/W
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REG_TCR = 0x06, // Transmission Control Register R/W
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REG_TLR = 0x07, // Trigger Level Register R/W
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REG_TXLV = 0x08, // Transmitter FIFO Level register Read
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REG_RXLV = 0x09, // Receiver FIFO Level register Read
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REG_IODIR = 0x0A, // Programmable I/O pins Direction register R/W
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REG_IOSTATE = 0x0B, // Programmable I/O pins State register R/W
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REG_IOINTENA = 0x0C, // I/O Interrupt Enable register R/W
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REG_IOCONTROL = 0x0E, // I/O Control register R/W
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REG_EFCR = 0x0F, // Extra Features Control Register R/W
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};
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// SC16IS752 Special register set
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enum : uint8_t{
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REG_DLL = 0x00, // Division registers R/W
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REG_DLH = 0x01, // Division registers R/W
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};
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// SC16IS752 Enhanced regiter set
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enum : uint8_t{
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REG_EFR = 0X02, // Enhanced Features Register R/W
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REG_XON1 = 0x04, // R/W
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REG_XON2 = 0x05, // R/W
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REG_XOFF1 = 0x06, // R/W
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REG_XOFF2 = 0x07, // R/W
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};
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};
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#endif // IO_I2CRailcom_h
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@ -337,12 +337,14 @@ bool TrackManager::setTrackMode(byte trackToSet, TRACK_MODE mode, int16_t dcAddr
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if (!canDo) {
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// if we discover that HA mode was globally impossible
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// we must adjust the trackPWM capabilities
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DIAG(F("High Accuracy & Railcom disabled"));
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FOR_EACH_TRACK(t) {
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track[t]->trackPWM=false;
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//DIAG(F("Track %c trackPWM 0 (global override)"), t+'A');
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}
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DCCTimer::clearPWM(); // has to be AFTER trackPWM changes because if trackPWM==true this is undone for that track
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}
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else DIAG(F("High Accuracy Enabled"));
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#else
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// For ESP32 we just reinitialize the DCC Waveform
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DCCWaveform::begin();
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