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STM32 I2C Clock selection for 100/400KHz
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pmantoine
parent
4f43a413b5
commit
e51f8e9c0a
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@ -26,34 +26,42 @@
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#include "I2CManager.h"
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#include "I2CManager_NonBlocking.h" // to satisfy intellisense
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//#include <avr/io.h>
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//#include <avr/interrupt.h>
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#include <wiring_private.h>
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#include "stm32f4xx_hal_rcc.h"
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/***************************************************************************
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* Interrupt handler.
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* IRQ handler for SERCOM3 which is the default I2C definition for Arduino Zero
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* compatible variants such as the Sparkfun SAMD21 Dev Breakout etc.
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* Later we may wish to allow use of an alternate I2C bus, or more than one I2C
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* bus on the SAMD architecture
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***************************************************************************/
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/*****************************************************************************
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* STM32F4xx I2C native driver support
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*
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* Nucleo-64 and Nucleo-144 boards all use I2C1 as the default I2C peripheral
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* Later we may wish to support other STM32 boards, allow use of an alternate
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* I2C bus, or more than one I2C bus on the STM32 architecture
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*****************************************************************************/
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#if defined(I2C_USE_INTERRUPTS) && defined(ARDUINO_ARCH_STM32)
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#if defined(ARDUINO_NUCLEO_F411RE) || defined(ARDUINO_NUCLEO_F446RE) || defined(ARDUINO_NUCLEO_F412ZG) || defined(ARDUINO_NUCLEO_F429ZI) || defined(ARDUINO_NUCLEO_F446ZE)
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// Assume I2C1 for now - default I2C bus on Nucleo-F411RE and likely all Nucleo-64
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// and Nucleo-144variants
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I2C_TypeDef *s = I2C1;
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// In init we will ask the STM32 HAL layer for the configured APB1 clock frequency in Hz
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uint32_t APB1clk1; // Peripheral Input Clock speed in Hz.
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uint32_t i2c_MHz; // Peripheral Input Clock speed in MHz.
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// IRQ handler for I2C1, replacing the weak definition in the STM32 HAL
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extern "C" void I2C1_EV_IRQHandler(void) {
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I2CManager.handleInterrupt();
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}
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extern "C" void I2C1_ER_IRQHandler(void) {
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I2CManager.handleInterrupt();
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}
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#else
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#warning STM32 board selected is not yet supported - so I2C1 peripheral is not defined
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#endif
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#endif
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// Assume I2C1 for now - default I2C bus on Nucleo-F411RE and likely Nucleo-64 variants
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I2C_TypeDef *s = I2C1;
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#define I2C_IRQn I2C1_EV_IRQn
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// Peripheral Input Clock speed in MHz.
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// For STM32F446RE, the speed is 45MHz. Ideally, this should be determined
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// at run-time from the APB1 clock, as it can vary from STM32 family to family.
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#define I2C_PERIPH_CLK 45
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// #define I2C_PERIPH_CLK 45
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// I2C SR1 Status Register #1 bit definitions for convenience
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// #define I2C_SR1_SMBALERT (1<<15) // SMBus alert
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@ -97,8 +105,6 @@ enum {TS_IDLE,TS_START,TS_W_ADDR,TS_W_DATA,TS_W_STOP,TS_R_ADDR,TS_R_DATA,TS_R_ST
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* that it is only called at the beginning of an I2C transaction.
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***************************************************************************/
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void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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return;
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// Calculate a rise time appropriate to the requested bus speed
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// Use 10x the rise time spec to enable integer divide of 50ns clock period
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uint16_t t_rise;
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@ -106,13 +112,9 @@ void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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while (s->CR1 & I2C_CR1_STOP); // Prevents lockup by guarding further
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// writes to CR1 while STOP is being executed!
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// Disable the I2C device, as TRISE can only be programmed whilst disabled
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s->CR1 &= ~(I2C_CR1_PE); // Disable I2C
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// Software reset the I2C peripheral
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// s->CR1 |= I2C_CR1_SWRST; // reset the I2C
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// delay(1);
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// Release reset
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// s->CR1 &= ~(I2C_CR1_SWRST); // Normal operation
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if (i2cClockSpeed > 100000L)
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{
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@ -127,19 +129,20 @@ void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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t_rise = 1000; // nanoseconds
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}
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// Configure the rise time register
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s->TRISE = t_rise * I2C_PERIPH_CLK / 1000UL + 1;
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s->TRISE = (t_rise / (1000 / i2c_MHz)) + 1;
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// Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
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// Bit 14: Duty, fast mode duty cycle (use 2:1)
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// Bit 11-0: FREQR = 16MHz => TPCLK1 = 62.5ns
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// Bit 11-0: FREQR
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if (i2cClockSpeed > 100000L) {
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// In fast mode, I2C period is 3 * CCR * TPCLK1.
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ccr_freq = I2C_PERIPH_CLK * 1000000 / 3 / i2cClockSpeed;
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s->CCR = (uint16_t)ccr_freq | 0x8000; // We need Fast Mode set
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//APB1clk1 / 3 / i2cClockSpeed = 38, but that results in 306KHz not 400!
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ccr_freq = 30; // So 30 gives 396KHz or so!
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s->CCR = (uint16_t)(ccr_freq | 0x8000); // We need Fast Mode set
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} else {
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// In standard mode, I2C period is 2 * CCR * TPCLK1.
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ccr_freq = I2C_PERIPH_CLK * 1000000 / 2 / i2cClockSpeed;
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s->CCR = (uint16_t)ccr_freq;
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// In standard mode, I2C period is 2 * CCR * TPCLK1
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ccr_freq = (APB1clk1 / 2 / i2cClockSpeed); // Should be 225 for 45Mhz APB1 clock
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s->CCR |= (uint16_t)ccr_freq;
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}
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// Enable the I2C master mode
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@ -151,7 +154,10 @@ void I2CManagerClass::I2C_setClock(uint32_t i2cClockSpeed) {
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***************************************************************************/
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void I2CManagerClass::I2C_init()
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{
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// Setting up the clocks
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// Query the clockspeed from the STM32 HAL layer
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APB1clk1 = HAL_RCC_GetPCLK1Freq();
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i2c_MHz = APB1clk1 / 1000000UL;
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// Enable clocks
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;//(1 << 21); // Enable I2C CLOCK
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// Reset the I2C1 peripheral to initial state
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RCC->APB1RSTR |= RCC_APB1RSTR_I2C1RST;
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@ -181,7 +187,8 @@ void I2CManagerClass::I2C_init()
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s->CR2 &= 0xE000;
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// Set I2C peripheral clock frequency
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s->CR2 |= I2C_PERIPH_CLK;
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// s->CR2 |= I2C_PERIPH_CLK;
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s->CR2 |= i2c_MHz;
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// set own address to 00 - not used in master mode
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I2C1->OAR1 = (1 << 14); // bit 14 should be kept at 1 according to the datasheet
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@ -210,10 +217,14 @@ void I2CManagerClass::I2C_init()
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// Bit 15: I2C Master mode, 0=standard, 1=Fast Mode
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// Bit 14: Duty, fast mode duty cycle
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// Bit 11-0: so CCR divisor would be clk / 2 / 100000 (where clk is in Hz)
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s->CCR = I2C_PERIPH_CLK * 5;
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// s->CCR = I2C_PERIPH_CLK * 5;
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s->CCR &= ~(0x3000); // Clear all bits except 12 and 13 which must remain per reset value
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s->CCR |= (APB1clk1 / 2 / 100000UL); // i2c_MHz * 5;
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// s->CCR = i2c_MHz * 5;
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// Configure the rise time register - max allowed is 1000ns, so value = 1000ns * I2C_PERIPH_CLK MHz / 1000 + 1.
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s->TRISE = I2C_PERIPH_CLK + 1; // 1000 ns / 50 ns = 20 + 1 = 21
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// s->TRISE = I2C_PERIPH_CLK + 1; // 1000 ns / 50 ns = 20 + 1 = 21
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s->TRISE = i2c_MHz + 1;
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// Enable the I2C master mode
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s->CR1 |= I2C_CR1_PE; // Enable I2C
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