mirror of
https://github.com/DCC-EX/CommandStation-EX.git
synced 2024-12-23 21:01:25 +01:00
198 lines
6.5 KiB
C++
198 lines
6.5 KiB
C++
/*
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* © 2022 Paul M Antoine
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* © 2021 Mike S
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* © 2021-2022 Harald Barth
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* © 2021 Fred Decker
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* © 2021 Chris Harlow
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* © 2021 David Cutting
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* All rights reserved.
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*
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* This file is part of Asbelos DCC API
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*
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* This is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* It is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with CommandStation. If not, see <https://www.gnu.org/licenses/>.
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*/
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// ATTENTION: this file only compiles on a SAMD21 based board
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// Please refer to DCCTimer.h for general comments about how this class works
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// This is to avoid repetition and duplication.
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#ifdef ARDUINO_ARCH_SAMD
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#include "FSH.h" //PMA temp debug
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#include "DIAG.h" //PMA temp debug
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#include "DCCTimer.h"
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INTERRUPT_CALLBACK interruptHandler=0;
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void DCCTimer::begin(INTERRUPT_CALLBACK callback) {
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interruptHandler=callback;
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noInterrupts();
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// Timer setup - setup clock sources first
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REG_GCLK_GENDIV = GCLK_GENDIV_DIV(1) | // Divide 48MHz by 1
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GCLK_GENDIV_ID(4); // Apply to GCLK4
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while (GCLK->STATUS.bit.SYNCBUSY); // Wait for synchronization
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REG_GCLK_GENCTRL = GCLK_GENCTRL_GENEN | // Enable GCLK
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GCLK_GENCTRL_SRC_DFLL48M | // Set the 48MHz clock source
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GCLK_GENCTRL_ID(4); // Select GCLK4
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while (GCLK->STATUS.bit.SYNCBUSY); // Wait for synchronization
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REG_GCLK_CLKCTRL = GCLK_CLKCTRL_CLKEN | // Enable generic clock
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4 << GCLK_CLKCTRL_GEN_Pos | // Apply to GCLK4
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GCLK_CLKCTRL_ID_TCC0_TCC1; // Feed GCLK to TCC0/1
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while (GCLK->STATUS.bit.SYNCBUSY);
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// Assume we're using TCC0... as we're bit-bashing the DCC waveform output pins anyway
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// for "normal accuracy" DCC waveform generation. For high accuracy we're going to need
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// to a good deal more. The TCC waveform output pins are mux'd on the SAMD, and output
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// pins for each TCC are only available on certain pins
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TCC0->WAVE.reg = TCC_WAVE_WAVEGEN_NPWM; // Select NPWM as waveform
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while (TCC0->SYNCBUSY.bit.WAVE); // Wait for sync
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// Set the frequency
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TCC0->CTRLA.reg |= TCC_CTRLA_PRESCALER(TCC_CTRLA_PRESCALER_DIV1_Val);
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TCC0->PER.reg = CLOCK_CYCLES * 2;
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while (TCC0->SYNCBUSY.bit.PER);
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// Start the timer
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TCC0->CTRLA.bit.ENABLE = 1;
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while (TCC0->SYNCBUSY.bit.ENABLE);
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// Set the interrupt condition, priority and enable it in the NVIC
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TCC0->INTENSET.reg = TCC_INTENSET_OVF; // Only interrupt on overflow
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NVIC_SetPriority((IRQn_Type)TCC0_IRQn, 0); // Make this highest priority
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NVIC_EnableIRQ((IRQn_Type)TCC0_IRQn); // Enable the interrupt
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interrupts();
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}
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// Timer IRQ handlers replace the dummy handlers (in cortex_handlers)
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// copied from rf24 branch
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void TCC0_Handler() {
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if(TCC0->INTFLAG.bit.OVF) {
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TCC0->INTFLAG.bit.OVF = 1; // writing a 1 clears the flag
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interruptHandler();
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}
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}
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void TCC1_Handler() {
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if(TCC1->INTFLAG.bit.OVF) {
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TCC1->INTFLAG.bit.OVF = 1; // writing a 1 clears the flag
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interruptHandler();
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}
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}
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void TCC2_Handler() {
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if(TCC2->INTFLAG.bit.OVF) {
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TCC2->INTFLAG.bit.OVF = 1; // writing a 1 clears the flag
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interruptHandler();
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}
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}
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bool DCCTimer::isPWMPin(byte pin) {
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//TODO: SAMD whilst this call to digitalPinHasPWM will reveal which pins can do PWM,
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// there's no support yet for High Accuracy, so for now return false
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// return digitalPinHasPWM(pin);
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return false;
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}
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void DCCTimer::setPWM(byte pin, bool high) {
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// TODO: High Accuracy mode is not supported as yet, and may never need to be
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(void) pin;
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(void) high;
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}
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void DCCTimer::clearPWM() {
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return;
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}
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void DCCTimer::getSimulatedMacAddress(byte mac[6]) {
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volatile uint32_t *serno1 = (volatile uint32_t *)0x0080A00C;
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volatile uint32_t *serno2 = (volatile uint32_t *)0x0080A040;
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// volatile uint32_t *serno3 = (volatile uint32_t *)0x0080A044;
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// volatile uint32_t *serno4 = (volatile uint32_t *)0x0080A048;
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volatile uint32_t m1 = *serno1;
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volatile uint32_t m2 = *serno2;
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mac[0] = m1 >> 8;
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mac[1] = m1 >> 0;
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mac[2] = m2 >> 24;
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mac[3] = m2 >> 16;
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mac[4] = m2 >> 8;
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mac[5] = m2 >> 0;
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}
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volatile int DCCTimer::minimum_free_memory=__INT_MAX__;
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// Return low memory value...
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int DCCTimer::getMinimumFreeMemory() {
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noInterrupts(); // Disable interrupts to get volatile value
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int retval = freeMemory();
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interrupts();
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return retval;
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}
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extern "C" char* sbrk(int incr);
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int DCCTimer::freeMemory() {
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char top;
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return (int)(&top - reinterpret_cast<char *>(sbrk(0)));
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}
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void DCCTimer::reset() {
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__disable_irq();
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NVIC_SystemReset();
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while(true) {};
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}
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int ADCee::init(uint8_t pin) {
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return analogRead(pin);
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}
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/*
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* Read function ADCee::read(pin) to get value instead of analogRead(pin)
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*/
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int ADCee::read(uint8_t pin, bool fromISR) {
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int current;
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if (!fromISR) noInterrupts();
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current = analogRead(pin);
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if (!fromISR) interrupts();
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return current;
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}
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/*
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* Scan function that is called from interrupt
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*/
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void ADCee::scan() {
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}
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void ADCee::begin() {
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noInterrupts();
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// Set up ADC to do faster reads... default for Arduino Zero platform configs is 436uS,
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// and we need sub-100uS. This code sets it to a read speed of around 21uS, and for now
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// enables 10-bit mode, although 12-bit is possible
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ADC->CTRLA.bit.ENABLE = 0; // disable ADC
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while( ADC->STATUS.bit.SYNCBUSY == 1 ); // wait for synchronization
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ADC->CTRLB.reg &= 0b1111100011111111; // mask PRESCALER bits
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ADC->CTRLB.reg |= ADC_CTRLB_PRESCALER_DIV64 | // divide Clock by 64
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ADC_CTRLB_RESSEL_10BIT; // Result on 10 bits default, 12 bits possible
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ADC->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_1 | // take 1 sample at a time
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ADC_AVGCTRL_ADJRES(0x00ul); // adjusting result by 0
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ADC->SAMPCTRL.reg = 0x00; // sampling Time Length = 0
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ADC->CTRLA.bit.ENABLE = 1; // enable ADC
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while(ADC->STATUS.bit.SYNCBUSY == 1); // wait for synchronization
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interrupts();
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}
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#endif
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