mirror of
https://github.com/daniviga/django-ram.git
synced 2026-02-03 17:40:39 +01:00
Fix order in the DCC interfaces
This commit is contained in:
@@ -151,10 +151,10 @@ DECODER_INTERFACES = [
|
||||
(0, "Built-in"),
|
||||
(1, "NEM651"),
|
||||
(2, "NEM652"),
|
||||
(3, "NEM658 (Plux22)"),
|
||||
(3, "NEM658 (Plux16)"),
|
||||
(6, "NEM658 (Plux22)"),
|
||||
(4, "NEM660 (21MTC)"),
|
||||
(5, "NEM662 (Next18/Next18S)"),
|
||||
(3, "NEM658 (Plux16)"),
|
||||
]
|
||||
|
||||
MANUFACTURER_TYPES = [
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
# Generated by Django 6.0 on 2026-01-08 11:14
|
||||
# Generated by Django 6.0 on 2026-01-08 12:16
|
||||
|
||||
from django.db import migrations, models
|
||||
|
||||
@@ -19,10 +19,10 @@ class Migration(migrations.Migration):
|
||||
(0, "Built-in"),
|
||||
(1, "NEM651"),
|
||||
(2, "NEM652"),
|
||||
(3, "NEM658 (Plux22)"),
|
||||
(3, "NEM658 (Plux16)"),
|
||||
(6, "NEM658 (Plux22)"),
|
||||
(4, "NEM660 (21MTC)"),
|
||||
(5, "NEM662 (Next18/Next18S)"),
|
||||
(3, "NEM658 (Plux16)"),
|
||||
],
|
||||
null=True,
|
||||
),
|
||||
Reference in New Issue
Block a user